Jeroen Croon

An easy-to-use mismatch model for the MOS transistor

In this paper, a physics-based mismatch model is presented. It is demonstrated on a 0.18-/spl mu/m technology that a simple mismatch model can still be used to characterize deep-submicron technologies. The accuracy of the model is examined and found to be within 20% in the strong inversion region. Bulk bias dependence is modeled in a physical way. To extract the mismatch parameters, a weighted fit is introduced. It is shown that the width and length dependence of the mismatch parameters is given by the Pelgrom model.

Line edge roughness: characterization, modeling and impact on device behavior

Simple analytical expressions are presented, which calculate the impact of line edge roughness on MOSFET parameter fluctuations. It is experimentally demonstrated that LER has no impact on 80 nm gate length transistors. Simulations show LER to become significant for 32 nm channel length devices.

CMOS device optimization for mixed-signal technologies

This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenarios for CMOS technologies lead to strong degradation of analog transistor performance. As a result the combined optimization of digital and analog devices for system-on-a-chip applications will require increasingly elaborate process modifications. New device solutions such as metal gate integration and asymmetric (source-side-only) workfunction modification offer process options for future mixed-signal CMOS applications.

A comparison of extraction techniques for threshold voltage mismatch

In this paper commonly used extraction methods of MOSFET threshold voltage mismatch are compared. The V/sub T/ mismatch is extracted on the exact same device population by four independent characterization groups. Significant differences are observed, which are caused by differences in measurement setup and differences in extraction algorithm. The observed differences are analyzed. In addition merits and limitations of the various techniques are evaluated.

Physical modeling and prediction of the matching properties of MOSFETs

A physical model is presented that describes the matching properties of the MOS transistor. Fluctuations in channel doping, fixed oxide charge, gate doping, and oxide thickness are taken into account. A good agreement is demonstrated between the model and the mismatch in the drain current and transconductance of a 0.13 /spl mu/m technology. Fluctuations in the channel doping are found to be the dominating effect. These affect the transistor through the threshold voltage directly, and through Coulomb scattering. A prediction is made concerning the matching properties of future technologies. It is expected that the fluctuations in the threshold voltage remain constant at A/sub 0/(/spl Delta/V/sub T/)=3 mV/spl mu/m, independently of the technology generation.

Influence of Doping Profile and Halo Implantation on the Threshold Voltage Mismatch of a 0.13um CMOS Technology

The fluctuation mechanisms which determine the threshold voltage mismatch of a 0.13 investigated by varying the bulk bias. The correct doping profile, obtained by SIMS measurements, is included in the analysis. This leads theoretically to a 20-35 % lower threshold voltage mismatch than when the profile is assumed uniform. The experimental threshold voltage mismatch is significantly higher than the theoretical limit caused by doping fluctuations. This is caused by the halo implant, which is implanted through the gate. The fluctuation in this charge is not described by Poisson statistics. It is mainly caused by the random character of the poly-silicon gate material. By correlating threshold voltage mismatch to current factor mismatch it is shown that the halo implant also causes extra fluctuations in gate depletion.

A 0.35 /spl mu/m SiGe BiCMOS process featuring a 80 GHz f/sub max/ HBT and integrated high-Q RF passive components

A SiGe HBT, fabricated by means of selective epitaxy, and high-Q RF passive components have been integrated into a 0.35 /spl mu/m BiCMOS process. The HBT features an f/sub T/ of 50 GHz and f/sub max/ of 80 GHz at V/sub BC/=2 V. The npn transistors are integrated in a 0.35 /spl mu/m CMOS process with poly resistors, MIM capacitors and thick metal 4 on chip spiral inductors.

Experimental investigation of the impact of line-edge roughness on MOSFET performance and yield

This work experimentally investigates the impact of line-edge roughness (LER) on the intrinsic transistor performance of the MOS transistor. Examined gate lengths range down to 50 nm. To emphasize the impact of LER, transistors with extra rough poly gates are created by e-beam lithography. Assumptions of models, that describe the effects of LER, are tested on transistors with sinusoidal gate-shapes. For the first time, the impact of LER on transistor yield is reported.

Ge deep sub-micron pFETs with etched TaN metal gate on a high-k dielectric, fabricated in a 200mm silicon prototyping line

We report for the first time on deep sub-micron Ge pFETs with physical gate lengths down to 0.151 /spl mu/m. The devices are made using a silicon-like process flow, with a directly etched gate stack consisting of TaN gate on an ALD or MOCVD HfO/sub 2/ dielectric. Promising drive currents are found. Various issues such as the severe short channel effects (SCE), the increased diode leakage compared to Si and the high amount of interface states (N/sub it/) are addressed. The need for an alternative Ge substrate pre-treatment and subsequent high-k gate dielectric deposition to push EOT values below 1 nm is illustrated.

Experimental analysis of a Ge-HfO/sub 2/-TaN gate stack with a large amount of interface states

First, the quality of the Ge-HfO/sub 2/ interface of early MOS capacitors is studied. The characterization difficulties related to the introduction of germanium as substrate material are analyzed and can be subdivided in problems due to the initial low quality of the samples, and due to the different material properties as compared to silicon. It is concluded from measurements of CV-curves at low temperature, gated diodes, and conductance analysis, that a large number interface states prevents inversion for p-substrate capacitors and accumulation for n-substrate capacitors. The paper then briefly discusses the difficulties related to the characterization of early MOS transistors on germanium substrates. These difficulties are mainly caused by a large amount of junction leakage.