Gonçalo Gonçalves

Role of order and disorder on the electronic performances of oxide semiconductor thin film transistors

The role of order and disorder on the electronic performances of n-type ionic oxides such as zinc oxide, gallium zinc oxide, and indium zinc oxide used as active (channel) or passive (drain/source) layers in thin film transistors (TFTs) processed at room temperature are discussed, taking as reference the known behavior observed in conventional covalent semiconductors such as silicon. The work performed shows that while in the oxide semiconductors the Fermi level can be pinned up within the conduction band, independent of the state of order, the same does not happen with silicon. Besides, in the oxide semiconductors the carrier mobility is not bandtail limited and so disorder does not affect so strongly the mobility as it happens in covalent semiconductors. The electrical properties of the oxide films (resistivity, carrier concentration, and mobility) are highly dependent on the oxygen vacancies (source of free carriers), which can be controlled by changing the oxygen partial pressure during the deposition...

High mobility indium free amorphous oxide thin film transistors

High mobility bottom gate thin film transistors (TFTs) with an amorphous gallium tin zinc oxide (a-GSZO) channel layer have been produced by rf magnetron cosputtering using a gallium zinc oxide (GZO) and tin (Sn) targets. The effect of postannealing temperatures (200, 250, and 300°C) was evaluated and compared with two series of TFTs produced at room temperature (S1) and 150°C (S2) during the channel deposition. From the results, it was observed that the effect of postannealing is crucial for both series of TFTs either for stability as well as for improving the electrical characteristics. The a-GSZO TFTs (W∕L=50∕50μm) operate in the enhancement mode (n-type), present a high saturation mobility of 24.6cm2∕Vs, a subthreshold gate swing voltage of 0.38V/decade, a turn-on voltage of −0.5V, a threshold voltage of 4.6V, and an Ion∕Ioff ratio of 8×107, satisfying all the requirements to be used as active-matrix backplane.

Gallium–Indium–Zinc-Oxide-Based Thin-Film Transistors: Influence of the Source/Drain Material

During the last years, oxide semiconductors have shown that they will have a key role in the future of electronics. In fact, several research groups have already presented working devices with remarkable electrical and optical properties based on these materials, mainly thin-film transistors (TFTs). Most of these TFTs use indium-tin oxide (ITO) as the material for source/drain electrodes. This paper focuses on the investigation of different materials to replace ITO in inverted-staggered TFTs based on gallium-indium-zinc oxide (GIZO) semiconductor. The analyzed electrode materials were indium-zinc oxide, Ti, Al, Mo, and Ti/Au, with each of these materials used in two different kinds of devices: one was annealed after GIZO channel deposition but prior to source/drain deposition, and the other was annealed at the end of device production. The results show an improvement on the electrical properties when the annealing is performed at the end (for instance, with Ti/Au electrodes, mobility rises from 19 to 25 cm2/V ldr s, and turn-on voltage drops from 4 to 2 V). Using time-of-flight secondary ion mass spectrometry (TOF-SIMS), we could confirm that some diffusion exists in the source/drain electrodes/semiconductor interface, which is in close agreement with the obtained electrical properties. In addition to TOF-SIMS results for relevant elements, electrical characterization is presented for each kind of device, including the extraction of source/drain series resistances and TFT intrinsic parameters, such as (intrinsic mobility) and VTi (intrinsic threshold voltage).

Thin-film transistors based on p-type Cu2O thin films produced at room temperature

Copper oxide (Cu2O) thin films were used to produce bottom gate p-type transparent thin-film transistors (TFTs). Cu2O was deposited by reactive rf magnetron sputtering at room temperature and the films exhibit a polycrystalline structure with a strongest orientation along (111) plane. The TFTs exhibit improved electrical performance such as a field-effect mobility of 3.9 cm2/V s and an on/off ratio of 2×102.

Write-erase and read paper memory transistor

We report the architecture and the performances of a memory based on a single field-effect transistor built on paper able to write-erase and read. The device is composed of natural multilayer cellulose fibers that simultaneously act as structural support and gate dielectric; active and passive multicomponent amorphous oxides that work as the channel and gate electrode layers, respectively, complemented by the use of patterned metal layers as source/drain electrodes. The devices exhibit a large counterclockwise hysteresis associated with the memory effect, with a turn-on voltage shift between 1 and −14.5V, on/off ratio and saturation mobilities of about 104 and 40cm2V−1s−1, respectively, and estimated charge retention times above 14000h.

Insight on the SU-8 resist as passivation layer for transparent Ga2O3–In2O3–ZnO thin-film transistors

A nonvacuum and low temperature process for passivating transparent metal oxides based thin-film transistors is presented. This process uses the epoxy-based SU-8 resist which prevents device degradation against environmental conditions, vacuum or sputtering surface damage. The incorporation of SU-8 as a passivation layer is based on the ability of this polymer to provide features with high mechanical and chemical stability. With this approach, lithography is performed to pattern the resist over the active area of the device in order to form the passivation layer. The resulting transistors demonstrate very good electrical characteristics, such as μFE=61 cm2/V s, VON=−3 V, ON/OFF=4.4×109, and S=0.28 V/dec. Electrical behavior due to the SU-8/metal oxide interface characteristics is also reported on the basis of Fourier transform infrared analysis. In contrast, we demonstrate how sputtering of SiO2 as a passivation layer results in severely degraded devices that cannot be switched-off. In order to obtain pro...

Low-temperature sputtered mixtures of high-κ and high bandgap dielectrics for GIZO TFTs

— This paper discusses the properties of sputtered multicomponent amorphous dielectrics based on mixtures of high-κ and high-bandgap materials and their integration in oxide TFTs, with processing temperatures not exceeding 150°C. Even if Ta2O5 films are already amorphous, multicomponent materials such as Ta2O5—SiO2 and Ta2O5—Al2O3 allow an increase in the bandgap and the smoothness of the films, reducing their leakage current and improving (in the case of Ta2O5—SiO2) the dielectric/semiconductor interface properties when these dielectrics are integrated in TFTs. For HfO2- based dielectrics, the advantages of multicomponent materials are even clearer: while HfO2 films present a polycrystalline structure and a rough surface, HfO2—SiO2 films exhibit an amorphous structure and a very smooth surface. The integration of the multicomponent dielectrics in GIZO TFTs allows remarkable performance, comparable with that of GIZO TFTs using SiO2 deposited at 400°C by PECVD. For instance, with Ta2O5—SiO2 as the dielectric layer, field-effect mobility of 35 cm2/(V-sec), close to 0 V turn-on voltage, an on/off ratio higher than 106, a subthreshold slope of 0.24 V/dec, and a small/recoverable threshold voltage shifts under constant current (ID= 10 μA) stress during 24 hours are achieved. Initial results with multilayers of SiO2/HfO2—SiO2/SiO2 are also shown, allowing a lower leakage current with lower thickness and excellent device performance.

Oxide semiconductors: Order within the disorder

The effect is considered of order and disorder on the electrical and optical performance of ionic oxide semiconductors used to produce optoelectronic devices such as p–n heterojunction solar cells and thin-film transistors (TFTs). The results obtained show that p-type c-Si/a-IZO/poly-ZGO solar cells exhibit efficiencies above 14% in device areas of about 2.34 cm2, whereas amorphous oxide TFTs based on the Ga–Zn–Sn–O system demonstrate superior performance to the polycrystalline ZnO TFTs, with I ON/I OFF ratio exceeding 107, turn-on voltage below 1–2 V and saturation mobility above 25 cm2 V−1 s−1. In addition, preliminary data on a p-type oxide TFT based on the Zn–Cu–O system are presented.

Environmental, Optical, and Electrical Stability Study of Solution-Processed Zinc–Tin–Oxide Thin-Film Transistors

In this paper, we report the environmental, optical, and gate bias stress stability of amorphous zinc-tin-oxide (ZTO) thin-film transistors (TFTs) fabricated by sol-gel spin-coating method. The ZTO TFTs showed excellent environmental and optical stability. The threshold voltage stability of ZTO TFTs was sensitive to both positive and negative gate bias stress. Maximum threshold voltage shifting of +1.9 and -3.2 V was observed under a gate bias stress of +10 and -10 V, respectively, with no significant change to subthreshold swing value.

Current transport mechanism at metal–semiconductor nanoscale interfaces based on ultrahigh density arrays of p-type NiO nano-pillars

The present work focuses on a qualitative analysis of localised I-V characteristics based on the nanostructure morphology of highly dense arrays of p-type NiO nano-pillars (NiO-NPs). Vertically aligned NiO-NPs have been grown on different substrates by using a glancing angle deposition (GLAD) technique. The preferred orientation of as grown NiO-NPs was controlled by the deposition pressure. The NiO-NPs displayed a polar surface with a microscopic dipole moment along the (111) plane (Taskers type III). Consequently, the crystal plane dependent surface electron accumulation layer and the lattice disorder at the grain boundary interface showed a non-uniform current distribution throughout the sample surface, demonstrated by a conducting AFM technique (c-AFM). The variation in I-V for different points in a single current distribution grain (CD-grain) has been attributed to the variation of Schottky barrier height (SBH) at the metal-semiconductor (M-S) interface. Furthermore, we observed that the strain produced during the NiO-NPs growth can modulate the SBH. Inbound strain acts as an external field to influence the local electric field at the M-S interface causing a variation in SBH with the NPs orientation. This paper shows that vertical arrays of NiO-NPs are potential candidates for nanoscale devices because they have a great impact on the local current transport mechanism due to its nanostructure morphology.