Göran Jerke

Electromigration-aware physical design of integrated circuits

The electromigration effect within current-density-stressed signal and power lines is an ubiquitous and increasingly important reliability and design problem in sub-micron IC designs. It is therefore necessary to consider electromigration-related design parameters as early as possible in the physical design flow. In this tutorial, we first give an introduction into the electromigration problem and its relationship to current density and temperature. Physical design parameters that affect current density are presented next. We then focus on various distinctive methodologies that allow the electromigration problem to be addressed directly during physical design and verification of both analog and digital circuits. We also present and discuss commercial applications of these electromigration-aware methodologies.

Current-driven wire planning for electromigration avoidance in analog circuits

Electromigration due to insufficient wire width can cause the premature failure of a circuit. The ongoing reduction of circuit feature sizes has aggravated the problem over the last couple of years, especially with analog circuits. It is therefore an important reliability issue to consider current densities already in the physical design stage. We present a new methodology capable of routing analog multi-terminal signal nets with current-dependent wire widths. It is based on current-driven wire planning which effectively determines all branch currents prior to detailed routing. We also discuss successful applications of our methodology in commercial analog circuit design.

Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits

Electromigration is caused by high current-density stress in the metallization patterns and is a major source of breakdown in electronic devices. It is, therefore, an important reliability issue to verify current densities within all stressed metallization patterns. In this paper, we propose an efficient methodology for hierarchical verification of current densities in arbitrarily shaped custom-circuit layouts as commonly used in analog circuits and analog blocks in mixed-signal ICs. Our approach includes a quasi-three-dimensional model to verify irregularities, such as vias and incorporates thermal simulation data to account for the temperature dependency of the electrical field configuration and the electromigration process. The described methodology, which can be integrated into any IC design flow as a design rule check, has been successfully tested and verified in commercial design flows.

A constraint-driven methodology for placement of analog and mixed-signal integrated circuits

Layout design of analog and mixed-signal circuits is often a manual and time-consuming, trial-and-error task. Stringent constraints that must be considered simultaneously are a major reason why layout design is often not automated. To overcome this bottleneck in the design process, we present a new constraint-driven design methodology. We have verified our methodology by applying it to the placement of both analog and mixed-signal circuits. Our approach allows us to verify whether a solution that satisfies all constraints exists prior to the time consuming optimization process. If a solution exists, an initial placement with a maximum constraint robustness is constructed. Next, the initial placement is optimized. Unlike the optimization engines known so far, our implementation is driven not only by the placement objectives, but also by the adaptively weighted constraints. This allows efficient searching in the solution space of the constraints.

Constraint-Driven Design Methodology: A Path to Analog Design Automation

Physical design for analog ICs has not been automated to the same degree as digital IC design, but such automation can significantly improve the productivity of circuit engineers. Analog design remains difficult to formalize due to a large amount of expert knowledge involved, such as sophisticated constraints that are specified manually and satisfied through manual layout. We therefore propose a constraint-driven design methodology – a suite of algorithms and methodologies to capture key rules governing analog layouts and to produce layouts that satisfy these rules. In this chapter, we identify major challenges in analog physical design, and relate them to constraints.We introduce techniques for constraint representation and highlight the essential components of a constraint-driven design methodology. Finally, we explain how constraint-driven design impacts a typical analog design flow, layout algorithms, and the overall physical design methodology.

On the verification of high-order constraint compliance in IC design

The increasing quality requirements on safety-critical electronic components and the rapid technological progress necessitate the compliance with all specified functional and non-functional design constraints. This paper introduces a novel verification method based on an unified data representation of constraints to enable multi-tool verification tasks. A constraint engineering system is presented which provides flexible, extensible, and multi-tool definitions of complex constraints and high-order verification tasks. Existing verification and simulation tools are combined so that the achieved complexity level of the high-order verification by far exceeds the level of the single tools. The shown examples target practical applications in analog system design and demonstrate the flexibility and the potential of this new verification approach.

Extended constraint management for analog and mixed-signal IC design

The consideration of a growing number of design constraints is becoming a bottleneck in the design of analog and mixed-signal integrated circuits and is blocking more, much-needed automation in this area. In this paper, we propose a solution to these issues with a new methodology for constraint propagation and transformation. This technique allows designers and software tools to consider all relevant constraints when modifying a design, regardless of where these constraints were originally created. We integrated our ideas in an industrial design flow. The implementation of an electrical constraint type demonstrates the practical relevance. With constraints of this type the ON resistance of power stages in smart power ICs can be limited for the first time.

Hierarchical propagation of geometric constraints for full-custom physical design of ICs

In industrial environments, full-custom layout design of analog and mixed-signal ICs is done hierarchically. In order to increase design efficiency, cell layouts are reused in the design hierarchy. Constraints forming relations between instances in different hierarchical contexts are of critical importance. While implementing a cell layout, these constraints have to be available in the cells context. In this paper, a general definition of hierarchical constraints for a constraint-driven design flow is given. Furthermore it is shown, how top-down declared constraints can be propagated into another hierarchical context. Only by propagation they become visible and verifiable for bottom-up cell design. The feasibility of our proposed methodology is shown by applying it to a modular Smart Power IC of the automotive industry.

Early-stage determination of current-density criticality in interconnects

Excessive current density within interconnects is a major concern for IC designers, which if not effectively mitigated leads to electromigration and electrical overstress. This is increasingly a problem in modern ICs due to smaller feature sizes and higher currents associated with lower supply voltages. Detailed analysis of all interconnect nets is both time-consuming and cannot be done until physical design is complete, when it is too late for easy fixes. To address these problems, we introduce (i) a powerful terminal current model and (ii) an efficient methodology to determine the worst-case bounds on segment currents of the interconnect. This early-stage calculation enables nets to be separated into critical and non-critical sets; only the set of critical nets, which is typically considerably smaller, requires subsequent special consideration during physical design and layout verification due to current density design limits. The presented algorithms are fast enough to run on every net, and work with known and unknown net topology, leading to several practical uses, such as (i) the pre-layout identification of nets that are potentially troublesome and may need sizing, (ii) as filter to avoid time-consuming detailed current-density analysis of net layouts, and (iii) to evaluate the effect of interconnect temperature and process changes on the number and distribution of current-density-critical nets.

Analog layout automation via self-organization: Enhancing the novel SWARM approach

This paper enhances SWARM, a novel deterministic analog layout automation approach based on the idea of cellular automata. SWARM implements a decentralized interaction model in which responsive layout modules, covering basic circuit types, autonomously move, rotate and deform themselves to let constraint-compliant, compact layout solutions emerge from a synergetic flow of self-organization. With the ability to consider design constraints both implicitly and explicitly, SWARM joins the layout quality of procedural generators with the flexibility of optimization algorithms, combining these two kinds of automation into a “bottom-up meets top-down” flow. The new enhancements are demonstrated in an OTA example, depicting the power of SWARM and its enormous potential for future developments.