Goran Lj. Djordjevic

TFMAC: Multi-channel MAC Protocol for Wireless Sensor Networks

In this paper we introduce TFMAC, a hybrid MAC protocol especially designed for wireless sensor networks in which each sensor node is equipped with a single half-duplex transceiver with multiple-frequency support. TFMAC incorporates multiple channels into a traditional TDMA scheme allowing different sensor nodes in a neighborhood to transmit on different channels simultaneously. Simulation results demonstrate that the proposed multiple-channel protocol provides higher maximum throughput and smaller average packet delay in respect to the basic single-channel TDMA scheme.

A heuristic for scheduling task graphs with communication delays onto multiprocessors

Abstract The multiprocessor scheduling problem can be stated as finding a schedule for a task graph to be executed on a multiprocessor architecture so that the execution time can be minimized. Since this problem is known to be NP-hard, in all but a few very restricted cases, the main research efforts in this area are focused on heuristic methods for obtaining near-optimal solutions in a reasonable amount of time. A new compile-time single-pass multiprocessor scheduling technique, called chaining , has been developed and is presented in this paper. Chaining takes into account the communication overhead and can be applied to scheduling task graphs onto fully-connected multiprocessor architectures containing an arbitrary (bounded as well as an unbounded) number of processors. This technique can be viewed as a generalized list scheduling concept, that does not impose any preconditions about the ordering in which tasks are selected for scheduling as well as about the position within the current partial schedule where selected task can be placed. Varying the selection policy, implemented in this technique, we are able to generate a class of scheduling algorithms. As a representative example of this class we present Task Selection First (TSF) scheduler. We compare performances of the TSF scheduler with the dynamic level scheduler proposed by Sih and Lee, the dominant sequence clustering algorithm proposed by Yang and Gerasoulis, and the DSC/MLS algorithm, a modified version of Sarkars two-step scheduling technique.

Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits

Abstract Very large scale integration (VLSI) technology has evolved to a level where large systems, previously implemented as printed circuit boards with discrete components, are integrated into a single integrated circuit (IC). But aggressive new chip design technologies frequently adversely affect chip reliability during functional operation. The use of a concurrent error detection (CED) scheme in order to achieve the high reliability requirement of modern computer systems is becoming an important design technique. The present paper describes implementations of separable codes for CED within VLSI ICs based on VHDL descriptions. Four schemes for concurrent error detection are analyzed: duplication of a combinational logic, Berger codes, Bose-Lin codes, and parity-check codes. Results concerning area overheads and operating speed decreases for 18 circuits, when they are implemented in FPGA and CPLD technologies, are reported.

CDMA bus-based on-chip interconnect infrastructure

Abstract As technology scales toward deep submicron, the integration of complete system-on-chip (SoC) designs consisting of large number of Intellectual Property (IP) blocks (cores) on the same silicon die is becoming technically feasible. Until recently, the design-space exploration for SoCs has been mainly focused on the computational aspects of the problem. However, as the number of IP blocks on a single chip and their performance continue to increase, a shift from computation-based to communication-based designs becomes mandatory. As a result, the communication architecture plays a major role in the area, performance and energy consumption of the overall systems [Pasricha S, Dutt N. On-chip communication architectures: system on chip interconnect. Amsterdam: Elsevier Inc.; 2008, Kim J, Verbauwhede I, Chang MCF. Design of an interconnect architecture and signaling technology for parallelism in communication. IEEE Trans VLSI Syst 2007;15(8):881–94]. This article presents a structure of a wrapper as a component of Code Division Multiple Access, CDMA, based shared bus architecture in a SoC. Two types of wrappers can be identified, master and slave. A master wrapper is located between the arbiter and CDMA coded physical interconnect, while a slave connects the CDMA coded bus with memory/peripheral module. In the proposal, only bus lines that carry address and data signals are CDMA coded. We implemented a pair of master–slave wrapper described in VHDL and confirmed its functionality using testbenches. Also we synthesized wrappers using a Xilinx Spartan and Virtex devices to determine resource requirements in respect to a number of equivalent gates, communication bandwidth, latency and power consumption. Specifically we involved a Design_Quality, DQ , metric for wrapper performance evaluation. A pair of master–slave wrapper seems to occupy appropriate space, in average 2000 equivalent gates, considering CPU cost of about 30,000 gates, what is less than 8% of hardware overhead per CPU. We also present experimental results which show that benefits of involving CDMA coding relates both to decreasing a number of bus lines and accomplishing simultaneous multiple master–slave connections at relatively low-power consumption and high communication bandwidth. Convenient range indices R W and R R to determine data transfer rate for Write and Read operations in multiprocessor bus systems that use TDMA and CDMA data transfer techniques. The obtained results show that increased data transfer latencies involved by CDMA data transfer are compensated by simultaneous master–slave transfers.

Reduced‐frame TDMA protocols for wireless sensor networks

SUMMARY Time-division multiple-access (TDMA) is a common medium access control paradigm in wireless sensor networks. However, in its traditional form, the TDMA-based protocols suffer from low channel utilization and high message delay because of a long frame length needed to provide collision-free transmissions, which is particularly damaging in dense wireless sensor networks. In this paper, we investigate the performance and the energy efficiency of a class of TDMA-based protocols, called reduced-frame TDMA, where every TDMA slot is augmented with a short time period dedicated for carrier sense multiple access-based contention resolution mechanism. Because of their ability to dynamically resolve collisions caused by conflicting slot assignments, the reduced-frame TDMA protocols can be configured with any frame length, independently of node density. In addition, we present a distributed heuristic slot assignment algorithm that minimizes interslot interference in the presence of limited number of slots per frame. The simulation results indicate that the reduced-frame TDMA protocols significantly reduce the message delay and increase the maximum throughput without incurring significant penalty in energy efficiency compared with the traditional TDMA scheme. Copyright

Fuzzy ring-overlapping range-free (FRORF) localization method for wireless sensor networks

The sensor node localization with an acceptable accuracy is a fundamental and important problem for location-aware applications of wireless sensor networks (WSNs). Among numerous localization schemes proposed specifically for WSNs, the received signal strength (RSS) based range-free localization techniques have attracted considerable research interest for their simplicity and low cost. However, these techniques suffer from significant estimation errors due to low accuracy of RSS measurements influenced by irregular radio propagation. In order to cope with the problem of RSS uncertainty, in this paper we propose a fuzzy set-based localization method, called fuzzy ring overlapping range free (FROFR) localization. Similar to other area-based localization schemes, FRORF relies on beacon signals broadcasted by anchors to isolate a region of the localization space where the sensor node most probably resides. As an extension to the concept of ring-overlapping localization, FRORF first represents overlapping rings as fuzzy sets with ambiguous boundaries in contrast to fixed intervals of RSS values, and then generates fuzzy set of regions by intersecting rings from different fuzzy ring sets. The degrees of sensor node membership to regions in the fuzzy set of regions are used to determine the location estimate. The results obtained from simulations demonstrate that our solution improve localization accuracy in the presence of radio irregularity, and even for the case without radio irregularity.

Simultaneous data transfers over peripheral bus using CDMA technique

The need for an efficient interconnect architecture has been caused by continued increase of the required communication bandwidth and concurrency of small-scale digital systems. The issue of applying the code division multiple access (CDMA) technique for data transfer over peripheral bus are discussed in this paper. The proposed technique represents an efficient interconnection solution for implementation in embedded systems based on low pin-count processing elements. Eight different system configurations, in respect to the number of transmitters and receivers, are realized at register-transfer level (RTL) using VHDL. The simulation results show that the communication bandwidth is scalable as the number of transmitter-receiver pairs increase.

Approach to partially self-checking combinational circuits design

This paper presents a cost-effective, non-intrusive technique of partially self-checking combinational circuits design. The proposed technique is similar to duplication with comparison, wherein duplicated function module and comparator act as a function checker that detects any erroneous response of the original function module. However, instead of realizing checker with full error-detection capability, we select a subset of erroneous responses to implement partial, but simplified function checker. A heuristic procedure that tries to find the optimal sum-of-product expression for partial function checker that minimizes its area while providing specified error coverage is described here. Effectiveness of the technique is evaluated on a set of MCNC 91 benchmark combinational circuits.

A Compile-Time Scheduling Heuristic for Multiprocessor Architectures

The multiprocessor scheduling problem can be stated as finding a schedule for a task graph to be executed on a multiprocessor architecture so that the execution time can be minimized. Since this problem is known to be NP-hard, in all but a few very restricted cases, the main research efforts in this area are focused on heuristic methods for obtaining near-optimal solutions in a reasonable amount of time. A new compile-time single-pass multiprocessor scneduling technique, called chaining, has been developed and is presented in this paper. Chaining can be used to schedule task graphs onto multiprocessor architectures that contain an arbitrary number of processors connected in an irregular fashion, taking into account the expected execution and communication requirements of the task graph on the given multiprocessor architecture. This technique can be viewed as a generalization of the list scheduling technique, that does not impose any preconditions about the ordering according to which tasks are selected for scheduling. Varying the selection criteria, implemented in this technique, we have generated a new class of scheduling algorithms. An evaluation of this class was made on 360 randomly generated examples, and the estimated performances were compared with two list scheduling algorithms, the dynamic level scheduler proposed by Sih and Lee, and the earliest task first algorithm proposed by Hwang et al.

VHDL-based design of FSM with concurrent error detection capability

This paper presents a VHDL-based methodology to design Self-Checking (SC) Finite State Machines (FSM). The methodology provides a library of pre-designed, parameterized concurrent error-detection (CED) modules as well as a VHDL code template that allow easily creation of synthesizable highlevel description of the SC FSM with minor additional design development time. The template offers selection of error-detecting schemes that will be used for encoding output data and states of the FSM. The generated SC FSM description can be simulated and synthesized with commercial tools. Effectiveness of the methodology is evaluated on a set of benchmark FSMs.