Mile K. Stojcev

Power management and energy harvesting techniques for wireless sensor nodes

Wireless sensor networks, WSNs, are large networks composed of small sensor nodes, SNs, with limited computer resources capable for gathering, data processing and communicating. Energy consumption represents a barrier challenge in many sensor network applications that require long lifetimes, usually an order of several years. Sensor nodes, as constituents of wireless sensor networks, are battery driven devices and operate on an extremely frugal energy budget. Conventional low-power design techniques and hardware architectures only provide partial solutions which are insufficient for sensor networks with energy-hungry sensors. This paper surveys several techniques used in todays wireless sensor networks with order to surpass the problem of energy consumption, power management and energy harvesting. It provides an insight into how various power reduction techniques can be used and orchestrated such that satisfactory performance can be achieved within a given energy budget.

Programmable jitter generator

As CMOS technology has scaled, supply voltage have dropped, chip power consumption has increased, and clock frequency/data rates increase effects of jitter become critical and jitter budget get tighter. Knowing how to inject/isolate jitter components with timeconvolution/correlation will enhance designer ability to determine and locate the root causes. Jitter can be decomposed into several subcomponents, each having specific sets of characteristics and root causes. This paper begins with a short review of jitter fundamentals. The jitter injection technique gives test engineers an insight into how jitter components interact. In the rest of the paper a global hardware structure of a jitter generator, which uses digital techniques, based on a voltage controlled delay line is described. A Xilinx xc3s500e-5fg320 FPGA chip is used to validate this design. The programmable jitter generator can be used in jitter tolerance test for computer system and jitter transfer function measurement in communication systems.

A mid-value select voter

Hardware redundancy may be used in a variety of manners to achieve fault tolerance. One of the most popular techniques is a triple modular redundancy (TMR) scheme. Such a scheme has also been referred to as masking redundancy because failures those affect only if one of the three modules is masked by the majority of the nonfailed modules. Most of the published works on TMR make one crucial assumption: In fault-free operation the outputs are equal. However it is well known that the output of redundant sensor elements in fault-tolerant data acquisition systems cannot be guaranteed to match even in fault-free operation. They are usually handled by a median-select or similar selection rule, so that redundant voter can pick a common value for processing by the rest of the system. This paper presents a VLSI fault-tolerant voter, with redundancy designed into the internal chip architecture. Instead of three we propose installation of four sensor elements. In order to insure that the voted value represents a correct consensus, we propose a mid-value hardware voting technique thanks to which we solve the problem of dissemination of each sensor element value to other ones. Finally, the effect of fault-tolerance on voter performance is discussed.

Current starved delay element with symmetric load

Variable delay elements are often used in different types of high-speed integrated circuits, mainly intended for delay compensation, skew equalization, etc. These circuits are normally realized as hybrid, composed of digital and analog controlled parts. The digital part is used for coarse-grain, while the analog for fine-grain delay variation. Efficient analog delay element architecture is proposed in this paper. The proposal is based on modification of the standard current starved delay element solution. An analytical equation that corresponds to the delay of the circuit is given also. In terms of control voltage, the proposed circuit has a linear delay transfer function in the whole range of regulation. Improvement is achieved at a cost of small hardware overhead in respect to the standard solution. Delay linearity error is less than 1% and the agreement between analytical model and simulation results is good, i.e. the error is less than 5%.

Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits

Abstract Very large scale integration (VLSI) technology has evolved to a level where large systems, previously implemented as printed circuit boards with discrete components, are integrated into a single integrated circuit (IC). But aggressive new chip design technologies frequently adversely affect chip reliability during functional operation. The use of a concurrent error detection (CED) scheme in order to achieve the high reliability requirement of modern computer systems is becoming an important design technique. The present paper describes implementations of separable codes for CED within VLSI ICs based on VHDL descriptions. Four schemes for concurrent error detection are analyzed: duplication of a combinational logic, Berger codes, Bose-Lin codes, and parity-check codes. Results concerning area overheads and operating speed decreases for 18 circuits, when they are implemented in FPGA and CPLD technologies, are reported.

Clock aligner based on delay locked loop with double edge synchronization

In CMOS multistage clock buffer design, the duty-cycle of clock is liable to be changed when the clock passes through several buffer stages. The pulse-width may be changed due to unbalance of the p- and n-OS transistors in the long buffer. This paper describes a delay locked loop with double edge synchronization for use in a clock alignment process. Results of its SPICE simulation, that relate to 1.2 μm CMOS technology, shown that the duty-cycle of the multistage output pulses can be precisely adjusted to (50 ± 1)% within the operating frequency range, from 55 MHz up to 166 MHz.

CDMA bus-based on-chip interconnect infrastructure

Abstract As technology scales toward deep submicron, the integration of complete system-on-chip (SoC) designs consisting of large number of Intellectual Property (IP) blocks (cores) on the same silicon die is becoming technically feasible. Until recently, the design-space exploration for SoCs has been mainly focused on the computational aspects of the problem. However, as the number of IP blocks on a single chip and their performance continue to increase, a shift from computation-based to communication-based designs becomes mandatory. As a result, the communication architecture plays a major role in the area, performance and energy consumption of the overall systems [Pasricha S, Dutt N. On-chip communication architectures: system on chip interconnect. Amsterdam: Elsevier Inc.; 2008, Kim J, Verbauwhede I, Chang MCF. Design of an interconnect architecture and signaling technology for parallelism in communication. IEEE Trans VLSI Syst 2007;15(8):881–94]. This article presents a structure of a wrapper as a component of Code Division Multiple Access, CDMA, based shared bus architecture in a SoC. Two types of wrappers can be identified, master and slave. A master wrapper is located between the arbiter and CDMA coded physical interconnect, while a slave connects the CDMA coded bus with memory/peripheral module. In the proposal, only bus lines that carry address and data signals are CDMA coded. We implemented a pair of master–slave wrapper described in VHDL and confirmed its functionality using testbenches. Also we synthesized wrappers using a Xilinx Spartan and Virtex devices to determine resource requirements in respect to a number of equivalent gates, communication bandwidth, latency and power consumption. Specifically we involved a Design_Quality, DQ , metric for wrapper performance evaluation. A pair of master–slave wrapper seems to occupy appropriate space, in average 2000 equivalent gates, considering CPU cost of about 30,000 gates, what is less than 8% of hardware overhead per CPU. We also present experimental results which show that benefits of involving CDMA coding relates both to decreasing a number of bus lines and accomplishing simultaneous multiple master–slave connections at relatively low-power consumption and high communication bandwidth. Convenient range indices R W and R R to determine data transfer rate for Write and Read operations in multiprocessor bus systems that use TDMA and CDMA data transfer techniques. The obtained results show that increased data transfer latencies involved by CDMA data transfer are compensated by simultaneous master–slave transfers.

Delay locked loop with linear delay element

Delay locked loops (DLLs) and phase locked loops (PLLs) are used in synchronous digital systems in order to improve timings, i.e. to minimize negative effects of skew and jitter in the clock distribution network. In this paper, we propose an efficient DLL architecture implemented with linear delay element. Linearization is achieved by modifying the classical hardware structures of the bias and charge pump circuits (Y. Moon et al., 2000). Namely, in our proposal both circuits, instead of single ended use differential input/output structure. This allows us to realize process independent and temperature compensated DLL circuit. Simulation results, that relate to models of 1.2 /spl mu/m CMOS double-poly double-metal technology, show that the proposed DLL has linear delay regulation and stable lock-in for supply voltage, temperature, and parameters technology process variations, in the full range of regulation.

Simultaneous data transfers over peripheral bus using CDMA technique

The need for an efficient interconnect architecture has been caused by continued increase of the required communication bandwidth and concurrency of small-scale digital systems. The issue of applying the code division multiple access (CDMA) technique for data transfer over peripheral bus are discussed in this paper. The proposed technique represents an efficient interconnection solution for implementation in embedded systems based on low pin-count processing elements. Eight different system configurations, in respect to the number of transmitters and receivers, are realized at register-transfer level (RTL) using VHDL. The simulation results show that the communication bandwidth is scalable as the number of transmitter-receiver pairs increase.

Approach to partially self-checking combinational circuits design

This paper presents a cost-effective, non-intrusive technique of partially self-checking combinational circuits design. The proposed technique is similar to duplication with comparison, wherein duplicated function module and comparator act as a function checker that detects any erroneous response of the original function module. However, instead of realizing checker with full error-detection capability, we select a subset of erroneous responses to implement partial, but simplified function checker. A heuristic procedure that tries to find the optimal sum-of-product expression for partial function checker that minimizes its area while providing specified error coverage is described here. Effectiveness of the technique is evaluated on a set of MCNC 91 benchmark combinational circuits.