Tatjana R. Nikolic

Programmable jitter generator

As CMOS technology has scaled, supply voltage have dropped, chip power consumption has increased, and clock frequency/data rates increase effects of jitter become critical and jitter budget get tighter. Knowing how to inject/isolate jitter components with timeconvolution/correlation will enhance designer ability to determine and locate the root causes. Jitter can be decomposed into several subcomponents, each having specific sets of characteristics and root causes. This paper begins with a short review of jitter fundamentals. The jitter injection technique gives test engineers an insight into how jitter components interact. In the rest of the paper a global hardware structure of a jitter generator, which uses digital techniques, based on a voltage controlled delay line is described. A Xilinx xc3s500e-5fg320 FPGA chip is used to validate this design. The programmable jitter generator can be used in jitter tolerance test for computer system and jitter transfer function measurement in communication systems.

CDMA bus-based on-chip interconnect infrastructure

Abstract As technology scales toward deep submicron, the integration of complete system-on-chip (SoC) designs consisting of large number of Intellectual Property (IP) blocks (cores) on the same silicon die is becoming technically feasible. Until recently, the design-space exploration for SoCs has been mainly focused on the computational aspects of the problem. However, as the number of IP blocks on a single chip and their performance continue to increase, a shift from computation-based to communication-based designs becomes mandatory. As a result, the communication architecture plays a major role in the area, performance and energy consumption of the overall systems [Pasricha S, Dutt N. On-chip communication architectures: system on chip interconnect. Amsterdam: Elsevier Inc.; 2008, Kim J, Verbauwhede I, Chang MCF. Design of an interconnect architecture and signaling technology for parallelism in communication. IEEE Trans VLSI Syst 2007;15(8):881–94]. This article presents a structure of a wrapper as a component of Code Division Multiple Access, CDMA, based shared bus architecture in a SoC. Two types of wrappers can be identified, master and slave. A master wrapper is located between the arbiter and CDMA coded physical interconnect, while a slave connects the CDMA coded bus with memory/peripheral module. In the proposal, only bus lines that carry address and data signals are CDMA coded. We implemented a pair of master–slave wrapper described in VHDL and confirmed its functionality using testbenches. Also we synthesized wrappers using a Xilinx Spartan and Virtex devices to determine resource requirements in respect to a number of equivalent gates, communication bandwidth, latency and power consumption. Specifically we involved a Design_Quality, DQ , metric for wrapper performance evaluation. A pair of master–slave wrapper seems to occupy appropriate space, in average 2000 equivalent gates, considering CPU cost of about 30,000 gates, what is less than 8% of hardware overhead per CPU. We also present experimental results which show that benefits of involving CDMA coding relates both to decreasing a number of bus lines and accomplishing simultaneous multiple master–slave connections at relatively low-power consumption and high communication bandwidth. Convenient range indices R W and R R to determine data transfer rate for Write and Read operations in multiprocessor bus systems that use TDMA and CDMA data transfer techniques. The obtained results show that increased data transfer latencies involved by CDMA data transfer are compensated by simultaneous master–slave transfers.

Simultaneous data transfers over peripheral bus using CDMA technique

The need for an efficient interconnect architecture has been caused by continued increase of the required communication bandwidth and concurrency of small-scale digital systems. The issue of applying the code division multiple access (CDMA) technique for data transfer over peripheral bus are discussed in this paper. The proposed technique represents an efficient interconnection solution for implementation in embedded systems based on low pin-count processing elements. Eight different system configurations, in respect to the number of transmitters and receivers, are realized at register-transfer level (RTL) using VHDL. The simulation results show that the communication bandwidth is scalable as the number of transmitter-receiver pairs increase.

Wrapper design for a CDMA bus in SOC

The research conducted in this paper is aimed at developing a CDMA shared bus as the efficient communication architecture for SOC. The main benefits of using this technique relate to reduction of the number of wires on system bus which varies from 25% up to 81%, while the main disadvantage is increase of the latency of processor read and write operations. The structure of a CDMA wrapper as an interface logic between the shared bus and IP connecting to it is described. VHDL models of two wrapper types (master and slave) are developed and verified. Four different implementations of the CDMA coding technique are presented and realized in FPGA and ASIC technologies.

Address generators for linear systolic array

Systolic arrays (SAs) are very efficient architectures for multimedia processing, database management, and scientific computing applications that are characterized by a high number of data access. However, in these data transfer and storage intensive applications, memory access is often the limiting factor to the computation speed. Since the memory subsystem dominates the cost (area), performance and power consumption of the SA, we have to pay a special attention to how memory subsystem can benefit from customization. In this paper we consider memory organization of linear systolic array with bi-directional links (called BLSA) suitable for implementation of broad class of algorithms. We assume that memory is organized into distributed smaller physical memory modules. In order to provide high bandwidth in data access we have designed special hardware, called address generator unit (AGU). The function of AGU is threefold. First, during the initialization, it transforms host address space into BLSA address space. Second, provides efficient memory data access during BLSA operation. Third, performs fast data transfer between BLSA and host at the end of the computation. In this article, we examine the impact on area and performance of memory access related circuity in eliminating computational intensive offset address calculations performed in software by implementing the needed address transformations with the AGUs. By involving hardware AGUs we achieved a speedup of approximately two, compared to the software implementation of address calculation, with a hardware overhead of only 7.6% in the worst case.

Low-power fault-tolerant interconnect method based on LCDMA and duplication

Abstract High computing capabilities and limited number of input/output pins of modern integrated circuits require an efficient and reliable interconnection architecture. The proposed communication scheme allows a large number of IP cores to send data over a single wire using logic code division multiple access (LCDMA) technique. Reliability is increased by using hardware redundancy, and three LCDMA-based fault tolerant designs are proposed: (a) duplication with logic comparison (DLC), (b) conventional triple modular redundancy (TMR), and (c) triple modular redundancy with sign voter (TSV). With aim to detect a received bit from chip sequence, LCDMA–DLC and LCDMA–TSV designs compare absolute values of the sums, while LCDMA–TMR compares only sign bits of the sums generated at the outputs of decoders. All proposed designs are implemented in FPGA and ASIC technologies. MATLAB simulation results show that increasing the length of spreading codes affects to an increase in reliability. A comparative analysis of the proposed fault tolerant designs in terms of hardware complexity, latency, power consumption and error detecting and correcting capability is conducted. It is shown that LCDMA–DLC design has lower hardware overhead and power consumption, with satisfactory better bit error rate (BER) performance, in comparison to LCDMA–TMR and LCDMA–TSV approach.

Reliable data transfer Rendezvous protocol in wireless sensor networks using 2D-SEC-DED encoding technique

Abstract Many applications in Wireless Sensor Networks (WSNs) require all data to be transmitted with minimal or without loss, what implies that reliability is an important characteristic. In any WSN, there are two basic approaches to recover erroneous packets. One way is to use Automatic Repeat reQuest (ARQ), and another is Forward Error Correction (FEC). The error-control systems for applications based on ARQ use error detection coupled with retransmission requests to maximize reliability at some cost to throughput. Error detection is generally provided by the lower protocol layers which use checksums (e.g. Cyclic Redundancy Checksums (CRCs)) to discard corrupted packets and trigger retransmission requests. In these solutions event a single erroneous bit can render a packet useless to the end user. Having in mind that in WSNs the power is scarce and is primarily consumed by wireless transmission and reception, we propose to use FEC rather than ARQ. FEC is a way of correcting packets by transmitting additional information bits with aim to reduce the frequency of retransmission requests. During this, data bytes are optionally encoded after being fragmented with Error Correcting Code (ECC) to recover data bits in case of small number of bit errors. Various FEC encoding schemes such as erasure and Hamming based codes are available. The choice of the encoding schemes depends on the applications and error characteristics (error models/patterns) of the wireless channel. Erasure encoding is preferable for usage when the error pattern is burst dominated, while Hamming encoding when noise causes random errors. Our observations show that most bit errors are single-bit or double-bit errors and burst errors are present but rare. In this work, an efficient Hamming based FEC encoding scheme of relatively low complexity called Two Dimensional-Single Error Correcting-Double Error Detecting (2D-SEC-DED), intended to minimize packet retransmissions and to save energy, has been developed. Such FEC scheme can be used to correct all single-bit and 99.99%of double/multiple-bit errors. Since the radio block is dominant energy consumer within a Sensor Node (SN), we focus our attention to answer the question: which is the adequate metric to use, and under what conditions to accurately characterize the quality of the communication, related to reliable data transfer, with minimal energy consumption. To this end, as first, in a case when the bit error is not high and most errors are single-bit, we show that 2D SEC-DED encoding scheme is more energy efficient in comparison to erasure encoding. As second, the advantages of using 2D-SEC-DED in respect to CRC (NO-FEC) encoding, concerning decreasing the energy consumption and increasing the reliability of the radio block are derived through implementation of two versions of the Rendezvous Protocol for Long Living (RPLL) referred as Modified-RPLL (M-RPLL as FEC based) and Ordinary-RPLL (O-RPLL as NO-FEC), respectively.

Using adaptive filtering in single-phase grid-connected system

Recently, there has been a pronounced increase of interest in the field of renewable energy. In this area power inverters are crucial building blocks in a segment of energy converters, since they change direct current (DC) to alternating current (AC). Grid connected power inverters should operate in synchronism with the grid voltage. In this paper, the structure of a power system based on adaptive filtering is described. The main purpose of the adaptive filter is to adapt the output signal of the inverter to the corresponding load and/or grid signal. By involving adaptive filtering the response time decreases and quality of power delivery to the load or grid increases. A comparative analysis which relates to power system operation without and with adaptive filtering is given. In addition, the impact of variable impedance of load on quality of delivered power is considered. Results which relates to total harmonic distortion (THD) factor are obtained by Matlab/Simulink software.

RECONFIGURABLE LOW POWER ARCHITECTURE FOR FAULT TOLERANT PSEUDO-RANDOM NUMBER GENERATION

High operating speed, fault tolerance (FT), low power and reconfiguration become today dominant issues during development and design of linear feedback shift registers (LFSRs), used as sequence generators, with randomness properties, in a process of testing complex CMOS VLSI ICs. In our design solution, we accomplish FT by using triple modular redundancy (TMR), i.e., a hardware scheme that uses spatial redundancy. For reduction of dynamic power consumption, clock-gating technique, as a simple and effective method, is implemented. The reconfigurable FPGA architecture provides us a feature to program and configure the degree of the primitive polynomial that the LFSR uses. High speed of operation, over 100 MHz, during testing is achieved by using circuits fabricated in submicron technology. An architecture which integrates in a single structure (IP core) all aforementioned design issues, named fault tolerant reconfigurable low-power pseudo-random number generator (FT_RLRG), is described in this article. The design of FT_RLRG is of practical interest in testing triple modular FT systems in the presence of single event upsets (SEUs), especially in a case when the design is SRAM-based. As an IP core the FT_RLRG has been implemented both on FPGA and ASIC technology. The main idea was to design a low-cost and low-power hardware structure which is able to adjust to any standards (past, present and future) operating at high-speed with different polynomials (currently up to 32nd order). The performance of FT_RLRG in respect to speed of operation (up to 150 MHz for FPGA and ASIC designs), low hardware overhead (0.033 mm2 area for ASIC and up to 530 slices for FPGA) and low-power consumption (0.45 mW for ASIC), for three different FPGA architecture (Spartan-3E, Virtex-4 and Virtex-6LP) and as an ASIC design implemented in 130 nm SiGe BiCMOS technology, have been estimated.

A fault-tolerant interconnections using LCDMA technique

The need for an efficient and reliable interconnect architecture has been caused by continual technology scaling and increased communication requirements. Using of the logic code division multiple access (LCDMA) and hardware redundancy techniques in order to achieve fault-tolerant interconnection with reduced number of wires, are discussed in this paper. Three different fault-tolerant interconnection approaches are considered: a) adding odd and even parity bit; b) duplication and comparison; and c) triple module redundancy. For BER simulation Matlab tool is used. Taking classical TDMA transmission as a referent one, the amount of BER increase for all three methods is derived. The obtained results show that the increase is within a range from several up to hundred times.