Gordon A. Russell

Optoelectronic interconnection technology in the HOLMS system

The High-Speed Optoelectronic Memory Systems (HOLMS) project, sponsored by the European Union Information Society Technology program, aims to make the use of board level optical interconnection in information systems practical and economical by developing optoelectronic packaging technology compatible with standard electronic assembly processes. To demonstrate the potential of the technology, we develop a demonstrator system that addresses the most pressing problem of contemporary computer architecture, memory latency. This paper describes the key ideas and some preliminary results of the HOLMS projects focusing on electronic interconnection technology, in particular optoelectronic packaging issues.

Design and construction of the high-speed optoelectronic memory system demonstrator

The high-speed optoelectronic memory system project is concerned with the reduction of latency within multiprocessor computer systems (a key problem) by the use of optoelectronics and associated packaging technologies. System demonstrators have been constructed to enable the evaluation of the technologies in terms of manufacturability. The system combines fiber, free space, and planar integrated optical waveguide technologies to augment the electronic memory and the processor components. Modeling and simulation techniques were developed toward the analysis and design of board-integrated waveguide transmission characteristics and optical interfacing. We describe the fabrication, assembly, and simulation of the major components within the system.

Free-space optical interconnected topologies for parallel computer application and experimental implementation using rapid prototyping techniques

Free-space optical interconnects (FSOIs) are widely seen as a potential solution to present and future bandwidth bottlenecks for parallel processors. We study different topologies that can be implemented using an FSOI system called optical highway (OH). We propose also the use of the rapid prototyping technique as a fast and low-cost tool to implement experimentally different topologies and study their properties. Finally, the rapid prototype designed is used to calculate the maximum number of stages that an optical signal can go through in the OH without the necessity of being regenerated.

Supporting Bulk Synchronous Parallelism with a high‐bandwidth optical interconnect

The list of applications requiring high‐performance computing resources is constantly growing. The cost of inter‐processor communication is critical in determining the performance of massively parallel computing systems for many of these applications. This paper considers the feasibility of a commodity processor‐based system which uses a free‐space optical interconnect. A novel architecture, based on this technology, is presented. Analytical and simulation results based on an implementation of BSP (Bulk Synchronous Parallelism) are presented, indicating that a significant performance enhancement, over architectures using conventional interconnect technology, is possible. Copyright

Optimization of reconfigurable optically interconnected systems for parallel computing

This paper examines the use of an FPGA to circumvent the redundancy that may occur in free-space optically interconnected systems. We believe this paper presents solutions to the mapping of emitters and detectors onto an optoelectronic interface in order to perform an efficient connection topology. We report a novel versatile arrangement of the input/output optical interface and a straightforward algorithm for the implementation of a completely connected topology. Both utilize the reconfigurable potential of the FPGA to ease the design constraints on the optical system.

Architectural limits on optical-highway-based parallel computing

The high bandwidth available in optoelectronic interconnects is often suggested as making them suitable for use in high-performance computer systems. However, it will be shown that for problems where message sizes are small, the latency of an optoelectronic interprocessor interconnect will place a lower limit on the number of processors required to produce performance enhancement over a traditional electronic interconnect.

Architecture and tolerancing for a matrix operation on the optical highway

An optical highway for parallel interconnection of processors has previously been presented. Several matrix-vector multiplication algorithms are mapped onto the highway, and these are compared with traditional results. The practicalities of implementing such a design are then discussed with attention to possible fabrication routes and the polarization losses involved. This specifically involves mapping the parameter space of the angle of polarizing elements by a Monte Carlo method.

Modelling an optically interconnected FPGA for reconfigurable computing architectures

A series of electronic models, both analog and digital, have been developed to simulate the behaviour of a field programmable gate array chip with optoelectronics providing access to an optical interconnect fabric. The minimum latency of a 320Mbits-1 system was found to be 158.5ns.