Keith J. Symington

Optoelectronic neural-network scheduler for packet switches

A novel, to our knowledge, type of packet scheduler that could significantly outperform current state-of-the-art schedulers is presented. The operation and the design of such a scheduler are discussed, and a fully operational experimental implementation is described. The scheduler uses a neural network in a winner-take-all strategy to optimize decisions on the throughput of both a crossbar and a banyan switching fabric. The problems of high interconnection density are solved by use of a free-space optical interconnect that exploits diffractive optical techniques to generate the required interconnection patterns and weights.

A neural-network packet switch controller: scalability, performance, and network optimization

We examine a novel combination of architecture and algorithm for a packet switch controller that incorporates an experimentally implemented optically interconnected neural network. The network performs scheduling decisions based on incoming packet requests and priorities. We show how and why, by means of simulation, the move from a continuous to a discrete algorithm has improved both network performance and scalability. The systems limitations are examined and conclusions drawn as to its maximum scalability and throughput based on todays technologies.

Experimental implementation of an optoelectronic neural network scheduler

We describe the design and successful operation of an optoelectronic Hopfield network demonstrator system. The Hopfield network, one of the simpler space-invariant interneuronal connection networks, was chosen due to its observed efficiency in solving optimization tasks. The demonstrator system, based around a free-space diffractive optical interconnect, was designed to perform a range of optimization tasks, in particular those associated with the scheduling of packets through different switching topologies. Experimental optimization of the neural network throughput, for both a crossbar and Banyan switch topology, allows the neural network parameters (e.g., neuron bias, neuron weighting) to be tuned to ensure optimal operation of the network for a particular switch topology. In addition, the demonstrator allows an investigation of the critical parameters governing the interoperation of the different modules. In this paper, we describe the effect of two of these parameters, namely, the operating temperature of the optoelectronic devices and the accuracy of the interconnection fabrication technology. The weighted interconnections in this optoelectronic system are provided by a diffractive optical element/lens combination whilst the neurons are implemented electronically. The transition between the electronic and optical domains is handled by an 8/spl times/8 VCSEL array for the electronic-optic interface, and an 8/spl times/8 Si photodetector array for the optic-electronic interface. The VCSEL array consists of oxide-confined near-infrared GaAs devices capable of 250-MHz modulation at a wavelength of 960 nm. The diffractive optical interconnect is designed using simulated annealing optimization and fabricated using very large scale integration photolithography. Using these techniques, it is possible to create interconnects with a total efficiency of /spl sim/70% and a nonuniformity of <1%.

Programmable optoelectronic neural network for optimization

An optoelectronic neural network is presented that is designed to solve the assignment problem--or any similar optimization task given minimal adjustment--in both crossbar and banyan packet switches. We examine the design decisions made at the hardware, software, and algorithmic levels and indicate the associated effect on the system as a whole. Clearly detailed experimental results show the systems robustness and performance due to the particular optoelectronic-algorithm combination used. The integration and packaging of such a system are also briefly discussed.

High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects

Optoelectronic interconnects are one means of alleviating the ever growing communications bottlenecks associated with silicon electronics. In chip-to-chip and board-to-board interconnection, the bandwidths presently (if experimentally) available far outstrip what is predicted possible in electronics until into the next decade. Such high bandwidth possibilities demand a rethink of conventional computer architectures where bandwidth is always at a premium. The combination of dynamic reconfiguration in electronics with this new technology may enable a new generation of architectures.

Optimization of reconfigurable optically interconnected systems for parallel computing

This paper examines the use of an FPGA to circumvent the redundancy that may occur in free-space optically interconnected systems. We believe this paper presents solutions to the mapping of emitters and detectors onto an optoelectronic interface in order to perform an efficient connection topology. We report a novel versatile arrangement of the input/output optical interface and a straightforward algorithm for the implementation of a completely connected topology. Both utilize the reconfigurable potential of the FPGA to ease the design constraints on the optical system.

Optoelectronic neural networks: mapping multilayer architectures on to an optoelectronic demonstrator

In this paper we outline some of the changes needed to implement multilayer feed-forward neural networks using the demonstrator hardware which was based on around an array of vertical cavity surface emitting lasers. Network simulations show that the neural network demonstrator hardware can be used to implement two different classes of feed-forward network, the multilayer perceptron (MLP) and radial basis function (RBF) networks. In both cases, the actual training of the networks is performed offline using hardware simulations and the weighted interconnections between neurons are fixed before application to the optoelectronic hardware.