John F. Snowdon

Optoelectronic interconnection technology in the HOLMS system

The High-Speed Optoelectronic Memory Systems (HOLMS) project, sponsored by the European Union Information Society Technology program, aims to make the use of board level optical interconnection in information systems practical and economical by developing optoelectronic packaging technology compatible with standard electronic assembly processes. To demonstrate the potential of the technology, we develop a demonstrator system that addresses the most pressing problem of contemporary computer architecture, memory latency. This paper describes the key ideas and some preliminary results of the HOLMS projects focusing on electronic interconnection technology, in particular optoelectronic packaging issues.

Optical Interconnectivity in a Scalable Data-Parallel System

Scalability. Few would disagree that the future of high-performance computing lies with massively parallel systems(MPS), since there are major physical limitations to the clockrate of a single processor. Massively parallel systems arerequired to be scalable in the sense that their performanceshould be proportional to the number of processors. However,a feasible architecture for a scalable massively parallel systemis still wanting, as true, i.e., unlimited scalability is not onlytheoretically impossible but even in the practical sense cannotbe achieved on a range of more than an order of magnitude inthe number of processors. Whatever a system’s architecture,interconnect, or programming model, something will not scale:the throughput or latency of the interconnect, its cost, orthe synchronization overheads. Since all these componentscontribute to performance in different ways, the issue of scal-ability is a very complex one indeed.So in what sense can one argue for scalability of massivelyparallel systems? There have been quite a few attempts todefine it (see [1]) on the basis of some strong assumptionsregarding the nature of parallel computation. The mostcommon assumption that is being made in such analyses is thatthe processors run some predominantly local processes whichrequire little external communication (it manifests itself in theparameter “communication to computation ratio” assumed tobe small and used in all but a few performance models). Bymigrating these self-contained processes and placing severalof them per processor to balance out computational workacross the system, it is believed that scalability may beachieved without requiring physically unfeasible networkingand/or dramatically different computational models. In reality,however, process concurrency of such kind continues to facevarious fundamental limitations from data mapping to dynamicload balancing to program paradigm issues.Data parallelism. We would like to address a simpler, andin our view more promising, way of doing parallel computing

Optoelectronic neural-network scheduler for packet switches

A novel, to our knowledge, type of packet scheduler that could significantly outperform current state-of-the-art schedulers is presented. The operation and the design of such a scheduler are discussed, and a fully operational experimental implementation is described. The scheduler uses a neural network in a winner-take-all strategy to optimize decisions on the throughput of both a crossbar and a banyan switching fabric. The problems of high interconnection density are solved by use of a free-space optical interconnect that exploits diffractive optical techniques to generate the required interconnection patterns and weights.

Development of free-space digital optics in computing

To someone with an electronics or computer science background, many of optical computings concepts may seem outlandish. Optics grew out of applied physics and still retains many aspects of that heritage. This is in contrast to digital computings roots in electronics. Recent efforts have been made to bring optical computing more in line with microelectronic engineering. Perhaps that will speed the acceptance of opto-electronic technology. The authors describe their research into optical devices for data communication. They are investigating free-space optics, the propagation of optical signals through the air using lenses and mirrors to focus and redirect the beams. The advantages of free-space optics, derive from their large spatial bandwidth and physical channel density. Like the human eye, which takes in an enormous amount of information in parallel, a low-cost lens can provide more than a million independent connections. The authors aim to exploit optoelectronic computings capability for such massively parallel data transfers.

A neural-network packet switch controller: scalability, performance, and network optimization

We examine a novel combination of architecture and algorithm for a packet switch controller that incorporates an experimentally implemented optically interconnected neural network. The network performs scheduling decisions based on incoming packet requests and priorities. We show how and why, by means of simulation, the move from a continuous to a discrete algorithm has improved both network performance and scalability. The systems limitations are examined and conclusions drawn as to its maximum scalability and throughput based on todays technologies.

Comparison of two approaches for implementing free-space optical interconnection networks

Abstract A particular design choice in the implementation of free-space optical interconnection networks (e.g. photonic backplanes) based on cascaded image-relay lenses is investigated. In these systems, a communication link can be implemented either by a single hop between source and destination nodes with the signal remaining in the optical domain through many image-relay stages, or by multiple hops between adjacent nodes with the signal undergoing optical–electrical conversion and vice versa at intermediate nodes (which act as repeaters). These two approaches place different demands on the optical system and the optoelectronic interface. We compare the raw bandwidth-per-link available in two example networks (the mesh and the completely connected network) using a model of the bandwidth and power consumption of an optoelectronic data channel and considerations on the aggregate bandwidth of the optoelectronic interface chip. We find that the single-hop approach provides a higher bandwidth-per-link. For example, the single-hop bandwidth-per-link is three times greater than the multiple-hop value for a mesh network of 49 nodes and for a completely connected network of 13 nodes. The advantage can increase further as the network size grows. The methodology is also applicable to the investigation of other implementation choices in optoelectronic interconnects.

Design and construction of the high-speed optoelectronic memory system demonstrator

The high-speed optoelectronic memory system project is concerned with the reduction of latency within multiprocessor computer systems (a key problem) by the use of optoelectronics and associated packaging technologies. System demonstrators have been constructed to enable the evaluation of the technologies in terms of manufacturability. The system combines fiber, free space, and planar integrated optical waveguide technologies to augment the electronic memory and the processor components. Modeling and simulation techniques were developed toward the analysis and design of board-integrated waveguide transmission characteristics and optical interfacing. We describe the fabrication, assembly, and simulation of the major components within the system.

Performance analysis of self-electro-optic-effect-device-based (SEED-based) smart-pixel arrays used in data sorting

The performance factors associated with self-electro-optic-effect-device-(SEED-) based smart-pixel arrays are analyzed in terms of semiconductor technology and pixel complexity. The sorting task is chosen as a practical example. Complementary metal-oxide semiconductor (CMOS)-SEED 2 × 2 self-routing nodes operated with quasi-cw-mode lasers are shown to provide the maximum processing power and on- or off-chip communication rate. The need for new front-end amplifiers for the smart-pixel technology is emphasized.

Construction and tolerancing of an optical-CLIP

An all-optical processing loop circuit, pumped entirely by semiconductor diode lasers, has been constructed and operated. Functional features include optically programmable logic, thresholding, and synchronization; these are achieved using three bistable interference filter devices. The circuit is presently single-channel, however 15 x 15 capability of the devices has been demonstrated using Dammann holograms and array-to-array coupling of a pair of bistable plates; potential parallelism is in excess of lO. Circuit simulations and tolerancing are also described.

Free-space optical interconnected topologies for parallel computer application and experimental implementation using rapid prototyping techniques

Free-space optical interconnects (FSOIs) are widely seen as a potential solution to present and future bandwidth bottlenecks for parallel processors. We study different topologies that can be implemented using an FSOI system called optical highway (OH). We propose also the use of the rapid prototyping technique as a fast and low-cost tool to implement experimentally different topologies and study their properties. Finally, the rapid prototype designed is used to calculate the maximum number of stages that an optical signal can go through in the OH without the necessity of being regenerated.