Sadok Aouini

Anti-Imaging Time-Mode Filter Design Using a PLL Structure With Transfer Function DFT

This paper presents a pole-zero placement approach for designing arbitrary-order time-mode filters for anti-imaging (reconstruction) applications. One application is for phase-domain sigma-delta modulation involving digital-to-time converters. The time-mode filters are constructed from an th-order type-II PLL single-loop feedback structure involving an active loop filter of order . The tradeoffs in terms of PLL order, noise bandwidth, settling- and lock-time, and the impact of the voltage-controlled oscillator (VCO) phase noise on the performance of the time-mode filter are investigated. A sixth-order PLL is designed and fabricated on a printed circuit board and is used to validate the proposed synthesis method. In addition, an all-digital phase stimulus generation method well suited to a digital scan-based design-for-test (DFT) approach for testing the frequency response behavior of time-mode filters and other PLL-based designs is proposed.

A low-cost ATE phase signal generation technique for test applications

In this article, an accurate and low-cost clock delay generation system integrated in an automated test equipment (ATE) environment is presented. The input to this system is entirely digital and is driven by a single clock, which can be programmed from the ATE High Speed Digital (HSD) unit. Moreover, the digital input patterns can easily be generated in software off-line; hence, making this system ideal for automated test routines. The system is first discussed and characterized in Matlab under static and dynamic operating conditions. For the static behavior, the impact of the various design tradeoffs on the time resolution is investigated. With regards to the dynamic behavior, the linearity is assessed spectrally with a sinusoidal input and statistically using a Gaussian noise signal. A discrete prototype board is built to validate the correct operation of the system mounted on an ATE to function as a whole. With proper compensation and calibration, a delay resolution of 15 ps was achieved over an 8.4 ns range using a low-speed reference clock running at 16.67 MHz. It is shown through clock scaling that this resolution can improve in direct proportion to increases in the clock frequency.

A Predictable Robust Fully Programmable Analog Gaussian Noise Source for Mixed-Signal/Digital ATE

A robust programmable analog Gaussian noise generator suitable for mixed-signal/digital ATEs is presented. Unlike conventional methods (LFSR based noise generators or resistor thermal noise amplification techniques), the user has full control of the characteristics of the Gaussian signal. Indeed, the frequency band, the mean, and variance of the distribution are fully programmable over the voltage range within the supply rails. The method consists of digitally encoding the specified Gaussian signal in a RAM, using pulse-density modulation, followed by filtering the bit stream using an analog low-pass filter. It is demonstrated that the quality of the generated noise signal is independent of the quality of the filter used; hence, making the noise source highly robust. The output of the noise generator accurately models a real Gaussian signal, even at high sigma values; thus, making it a very effective and predictable dithering signal. Two applications of the proposed Gaussian noise source are demonstrated: ADC histogram testing and high-resolution digitization

Mixed-Signal Production Test: A Measurement Principle Perspective

This article, based on a tutorial the author presented at ITC 2008, is an overview and introduction to mixed-signal production test. The article focuses on the fundamental techniques and procedures in production test and explores key issues confronting the industry.

An Overview of Mixed-Signal Production Test from a Measurement Principle Perspective

In this article, a tutorial on the techniques and procedures used in a production test environment is presented. This overview is structured in such a way that the less experienced test engineer can learn about the common and various methods used in mixed-signal test. Various aspects related to test and their role in the manufacturing process of ICs are discussed. In fact, the paper starts off by motivating the need for testing and then describes the different methods: DC, AC, and dynamic testing as well as clocks, SerDes and RF testing. Design for Test (DFT) techniques are also described.

A DFT Loopback Scheme for ADC ENOB Testing Using an All-Digital ATE

This article presents a design-for-test (DFT) loopback scheme for testing the analog portion of a mixed-signal chip using an all- digital tester. In fact, the proposed approach is used to assess the ENOB of a high-speed 6-bit ADC without the need for an external signal generator. Using an on-chip PLL with a programmable divider, a divided version of the 16GHz clock is passed through an on-chip buffer network where the output driver amplitude is programmable to achieve the desired fill ratio (~80%). The test PLL is coherent to the system PLL as they are driven from the same reference clock; hence, no windowing needs to be applied to the ADC output prior to performing the FFT for ENOB assessment. The on-chip output driver has an open-drain configuration that is far- end terminated through 50Ω pull-up resistors connected to a 2.0V external supply on the device interface board (DIB). The output is then applied to a 5th order external filter on the DIB with a 3dB cutoff frequency of 2.4GHz to filter out the high order harmonics prior to looping back the stimulus to the ADC front-end. The proposed scheme is implemented within a CMOS 32nm ADC macro and is experimentally validated using a commercial all-digital automated-test-equipment (ATE). A 4.5 bit ENOB was experimentally measured using the ADC under test. Unlike conventional loopback schemes, the proposed architecture is not susceptible to fault masking.

A 32-nm CMOS Frequency Locked Loop for 20-GHz Synthesis with ± 7.6 ppm Resolution

In this work, a digitally assisted frequency locked loop is implemented using 32-nm CMOS technology and acts as a 20-GHz frequency synthesizer. The frequency difference between the reference clock and the VCO output is obtained using a pair of 18- bit counters. Also, an offset value is added to the counter output to tune the VCO frequency in closed loop. The frequency synthesizer resolution is ± 7.6 p.p.m. over a measured locking range equal to 300 MHz.

Jitter generation and capture using phase-domain sigma-delta encoding

This article presents techniques and circuits for jitter generation and measurement. The proposed implementations use periodic bit-streams and high-order PLLs to generate the desired phase signal. Here, an arbitrary signal is first encoded using sigma-delta modulation in the digital amplitude-domain and converted to the phase-domain through a digital-to-time converter (DTC) process realized in software. The resulting bit-stream is inputted cyclically to a high-order phase-locked loop (PLL) behaving as a time-domain filter. The parameters of the sigma-delta modulator along with those of the high-order PLL can be traded for one another to achieve maximum performance. The method to generate the sigma-delta encoded phase signal and to design the high-order PLL is presented. A high quality Gaussian jitter signal has been experimentally generated. Also, a setup using DC encoded phase shifts serving as an under-sampling clock to measure jitter with a 50 GHz effective sampling rate has also been experimentally proven. The conciseness and digital nature of the jitter generation scheme together with the jitter measurement architecture makes them easily amenable to a design-for-test framework.

Generating Test Signals for Noise-Based NPR/ACPR Type Tests in Production

In this article, a low-cost, high-frequency signal generation procedure suitable for Noise Power Ratio (NPR) and Adjacent Channel Power Ratio (ACPR) test is presented. The proposed technique can be implemented with any ATE equipped with a memory block and digital source in conjunction with a high frequency and high attenuation analog filter; hence, a costly external source is not required. The technique consists of digitally encoding the noise signal having the specified power spectrum using pulse-density modulation and recovering the analog stimulus with an analog filter operating in the desired spectrum. The technique is validated by simulation and experimental results. In simulation, both NPR and ACPR stimulus were realized with a 100 dB specification. For NPR test stimulus generation, a notch depth of 60 dB with respect to the noise pedestal was experimentally achieved. The sensitivity of the proposed methodology to jitter is also investigated.