Ihab Amer

The Reconfigurable Video Coding Standard [Standards in a Nutshell]

More than two decades of research in digital video technologies, together with the emergence of successful international standards for digital video compression, have led to a wide variety of digital video products using video compression for professional and consumer applications. Although many of these video compression standards share common and/or similar coding tools, there is currently no explicit way to exploit such commonalities at the level of the specifications nor at the level of implementations. Moreover, the possibility of taking advantage of the benefits of the continuous improvements of coding technology is only possible by replacing an old standard with a new one. This usually results in the replacement of the existing multimedia devices with new ones capable of handling the new deployed standards. Such necessity is not always well accept-ed by the public and professionals for obvious reasons.

Reconfigurable video coding on multicore

This article provides an overview of the main objectives of the new RVC standard, with an emphasis on the features that enable efficient implementation on platforms with multiple cores. A brief introduction to the methodologies that efficiently map RVC codec specifications to multicore platforms is accompanied with an example of the possible breakthroughs that are expected to occur in the design and deployment of multimedia services on multicore platforms.

Reconfigurable Video Coding on Multicore: The Video Coding Standard for Multi-Core Platforms

This article provides an overview of the main objectives of the new RVC standard, with an emphasis on the features that enable efficient implementation on platforms with multiple cores. A brief introduction to the methodologies that efficiently map RVC codec specifications to multicore platforms is accompanied with an example of the possible breakthroughs that are expected to occur in the design and deployment of multimedia services on multicore platforms.

Towards MPEG-4 part 10 system on chip: a VLSI prototype for context-based adaptive variable length coding (CAVLC)

The paper presents a VLSI prototype for context-based adaptive variable length coding (CAVLC). This scheme is a part of the lossless compression process in the MPEG-4 Part 10 standard. It is applied to the quantized transform coefficients of the luminance component during the entropy coding process. In combination with previous transformations and quantizations, it can result in significantly increased compression ratio. The developed architecture is prototyped and simulated using ModelSim 5.4/spl reg/. It is synthesized using Synplify Pro 7.1/spl reg/. The results show that the architecture satisfies the real-time constraints required by different digital video applications.

A HIGH-PERFORMANCE HARDWARE IMPLEMENTATION OF THE H.264 SIMPLIFIED 8X8 TRANSFORMATION AND QUANTIZATION

The recently approved digital video standard known as H.264 promises to be an excellent video format for use with a large range of applications. Real-time encoding/decoding is a main requirement for adoption of the standard to take place in the consumer marketplace. Transformation and quantization in H.264 are relatively less complex than their correspondences in other video standards. Nevertheless, for real-time operation, a speedup is required for such processes. Especially after the recent proposal to use an 8/spl times/8 integer approximation of discrete cosine transform (DCT) to give significant compression performance at standard definition (SD) and high definition (HD) resolutions. This paper discusses a high-performance hardware implementation of the H.264 simplified 8/spl times/8 transformation and quantization. The results show that the architecture satisfies the real-time constraints required by different digital video applications.

A high-performance hardware implementation of the H.264 simplified 8×8 transformation and quantization [video coding]

The recently approved digital video standard known as H.264 promises to be an excellent video format for use with a large range of applications. Real-time encoding/decoding is a main requirement for adoption of the standard to take place in the consumer marketplace. Transformation and quantization in H.264 are relatively less complex than their correspondences in other video standards. Nevertheless, for real-time operation, a speedup is required for such processes. Especially after the recent proposal to use an 8/spl times/8 integer approximation of discrete cosine transform (DCT) to give significant compression performance at standard definition (SD) and high definition (HD) resolutions. This paper discusses a high-performance hardware implementation of the H.264 simplified 8/spl times/8 transformation and quantization. The results show that the architecture satisfies the real-time constraints required by different digital video applications.

A VLSI prototype for Hadamard transform with application to MPEG-4 part 10

This paper presents a VLSI prototype for the 2times2 Hadamard transform that is applied to the DC coefficients of the four 4times4 blocks of each chroma component as described in the MPEG-4 part 10 advanced video coding (AVC) standard. A VLSI prototype fir the quantization process that is accompanied with the transform operation is given as well. The implemented transform represents a level in the hierarchical transform adopted in the new AVC standard. The transform is computed using add operations only. This reduces the computational requirements of the design. The architecture is prototyped and simulated using ModelSim 5.4reg. It is synthesized using Leonardo Spectrumreg. The results show that the architecture satisfies the real-time constraints required by high definition television (HDTV)

CAL Dataflow Components for an MPEG RVC AVC Baseline Encoder

In this paper, an efficient H.264/AVC baseline encoder, described in RVC-CAL actor language, is introduced. The main aim of the paper is twofold: a) to demonstrate the flexibility and ease that is provided by RVC-CAL, which allows for efficient implementation of the presented encoder, and b) to shed light on the advantages that can be brought into the RVC framework by including such encoding tools. The main modules of the designed encoder include: Inter Frame Prediction (Motion Estimation/Compensation), Intra Frame Prediction, and Entropy Coding. Descriptions of the designed modules, accompanied with RVC-CAL design issues are provided. A comparison between different development approaches is also provided. The obtained results show that specifying complex video codecs (e.g. H.264/AVC encoder) using RVC-CAL followed by automatic translation into HDL, which is achievable by the tools that support the standard, results in more efficient HW implementation compared to the traditional HW design flow. A discussion that explains the reasons behind such results concludes the paper.

A hardware-accelerated framework with IP-blocks for application in MPEG-4

In this paper we present a hardware-accelerated framework and hardware blocks for MPEG-4 part 10 IP-quality assessment. We give examples of various IP-blocks that have been designed and tested on the integration platform. The hardware-accelerated framework enabled us to asses their quality along with the MPEG-4 part 10 software reference model.

On the way to an H.264 HW/SW reference model: a SystemC modeling strategy to integrate selected IP-blocks with the H.264 software reference model

SystemC is a new hardware design concept that enables the designer to perform early functional verification of developed hardware blocks by facilitating their integration with software in a unified platform. It provides hardware-oriented constructs within the context of C++ as a class library implemented in standard C++. In this paper, we propose a strategy that enables us to emulate a model of a full HW/SW H.264 encoder. The latest reference software is modified by allowing selected computationally extensive modules to be optionally executed in emulated hardware. SystemC is used for hardware modeling. The proposed strategy enables us to perform early functional verification and conformance analysis of the IP-blocks at the system level of abstraction.