Graham M. Megson

The locally twisted cubes

This paper introduces a new variant of the popular n-dimensional hypercube network Q n , known as the n-dimensional locally twisted cube LTQ n , which has the same number of nodes and the same number of connections per node as Q n . Furthermore, LTQ n is similar to Q n in the sense that the nodes can be one-to-one labeled with 0–1 binary sequences of length n, so that the labels of any two adjacent nodes differ in at most two successive bits. One advantage of LTQ n is that the diameter is only about half of the diameter of Q n . We develop a simple routing algorithm for LTQ n , which creates a shortest path from the source to the destination in O(n) time. We find that LTQ n consists of two disjoint copies of Q n −1 by adding a matching between their nodes. On this basis, we show that LTQ n has a connectivity of n.

On the maximal connected component of hypercube with faulty vertices (II)

Hypercube is one of the most popular topologies for connecting processors in multicomputer systems. In this paper we address the maximum order of a connected component in a faulty cube. The results established include several known conclusions as special cases. We conclude that the hypercube structure is resilient as it includes a large connected component in the presence of large number of faulty vertices.

Locally twisted cubes are 4-pancyclic

Abstract The locally twisted cube is a newly introduced interconnection network for parallel computing. Ring embedding is an important issue for evaluating the performance of an interconnection network. In this paper, we investigate the problem of embedding rings into a locally twisted cube. Our main contribution is to find that, for each integer l e {4, 5,… 2n}, a ring of length l can be embedded into an n-dimensional locally twisted cube so that both the dilation and the load factor are one. As a result, a locally twisted cube is Hamiltonian. We conclude that a locally twisted cube is superior to a hypercube in terms of ring embedding capability.

Honeycomb tori are Hamiltonian

The honeycomb torus is an alternative to the usual torus networks commonly used in parallel architectures. In this paper, we present algorithms for constructing Hamiltonian cycles in honeycomb tori. Such algorithms can be used to embed many structures into the honeycomb tori to provide efficient communication.

A comparison-based diagnosis algorithm tailored for crossed cube multiprocessor systems

Abstract Comparison-based diagnosis is an effective approach to system-level fault diagnosis. Under the Maeng–Malek comparison model (MM* model), Sengupta and Dahbura proposed an O(N5) diagnosis algorithm for general diagnosable systems with N nodes. Thanks to lower diameter and better graph embedding capability as compared with a hypercube of the same size, the crossed cube has been a promising candidate for interconnection networks. In this paper, we propose a fault diagnosis algorithm tailored for crossed cube connected multicomputer systems under the MM* model. By introducing appropriate data structures, this algorithm runs in O ( N log 2 2 N ) time, which is linear in the size of the input. As a result, this algorithm is significantly superior to the Sengupta–Dahburas algorithm when applied to crossed cube systems.

Synthesis of a systolic array genetic algorithm

The paper presents the design of a hardware genetic algorithm which uses a pipeline of systolic arrays. Demonstrated is the design methodology where a simple genetic algorithm expressed in C source code is progressively re-written into a recurrence form from which systolic structures can be deduced. The paper extends previous work by the authors by introducing a simplification to a previous systolic design.

Minimum neighborhood in a generalized cube

Generalized cubes are a subclass of hypercube-like networks, which include some hypercube variants as special cases. Let θG(k) denote the minimum number of nodes adjacent to a set of k vertices of a graph G. In this paper, we prove θG(k) ≥ -1/2;k2 + (2n - 3/2)k - (n2 - 2) for each n-dimensional generalized cube and each integer k satisfying n + 2 ≤ k ≤ 2n. Our result is an extension of a result presented by Fan and Lin [J. Fan, X. Lin, The t/k-diagnosability of the BC graphs, IEEE Trans. Comput. 54 (2) (2005) 176-184].

SYSTOLIC MATRIX INVERSION USING A MONTE CARLO METHOD

ABSTRACT A systolic array for inverting an n × n matrix using a Monte Carlo method is proposed. The basic array computes a single row of the inverse in 3n + N + T steps ( including input and output time) and O( nNT) cells where N is the number of chains and T is the length of each chain in the stochastic process. A full inverse is computed in the same time but requires O(n2NT) cells. Further improvements reduce the time to 3n/ 2 + N + T using the same number of cells. A number of bounds on N and T are established which show that our design is faster than existing designs for reasonably large values of n Indeed the final arrays require less than n4 cells and have a computing time bounded above by 4n.

FAULT-TOLERANT RING EMBEDDING IN A HONEYCOMB TORUS WITH NODE FAILURES

Honeycomb torus networks have been recognised as an attractive alternative to existing torus interconnection networks in parallel and distributed applications. In this paper we establish that there exists a hamiltonian cycle in a honeycomb torus with two adjacent faulty nodes and that with a single fault a ring embedding with one less node than the fault free torus can be found.

The systolic array genetic algorithm, an example of systolic arrays as a reconfigurable design methodology

We have designed and constructed a genetic algorithm engine using a systolic design methodology. The approach has a number of advantages. Firstly the design processes is systematic. A C source code version of the algorithm is used as a starting point and progressively the code is re-written into a form from where systolic cells can be designed. Secondly the modular nature of the arrays allow easy expansion of the design for different requirements (larger populations in this example). Hardware designs are re-used extensively and, in combination with reconfigurable computing techniques, can be swapped in or out on an application specific basis to construct arrays of the correct size. This can also be extended to swapping in and out whole elements of the macro-pipeline so that alternative operators, such as Tournament Selection can be employed. Thirdly, a traditional benefit of systolic arrays applies. The resultant design is massively parallel and significant throughput can be achieved.