Graham William Hills

Reverse pillar and maskless contact-two novel recessed metal schemes and their comparisons to conventional VLSI metallization schemes

Two novel metallization schemes, reverse pillar and maskless contact, based on the recessed metal approach, are discussed. The reverse-pillar process offers a self-aligned headless contact for optimum layout. The maskless contact scheme removes the need for a contact lithographic step. The schemes are compared to the conventional metallization schemes. Both the advantages and disadvantage of the schemes are discussed. Both schemes offer the advantages of planarization and easy integration into standard multilevel metal approaches.<<ETX>>

Superior metal step coverage and dielectric quality in a simple two-level metal 1.0 mu m CMOS technology

A two-level metal process for a fourth-generation 1.0- mu m CMOS technology has been developed which yields superior aluminum step coverages and high-quality dielectrics without introducing complicated processing sequences. The process is cost-effective since it includes traditional materials and high throughput operations and is readily extendable to three levels of metal. The process incorporates a highly smoothed BPSG for dielectric I and resist-etchback planarization of plasma-enhanced TEOS for dielectric II. Also featured are a tapered aluminum I profile and modified contact window and via etch profiles. Defect density and electromigration data predict excellent yield and reliability for this process.<<ETX>>

A high-performance submicron CMOS two-level metal technology incorporating a plasma CVD TEOS interlevel dielectric

The process technology for a fifth generation, high-performance, twin-tub, two-level metal, submicron CMOS technology designed for 5-V custom VLSI applications is presented. Features include high-pressure oxidation, lightly doped drain structures for both n and p channel devices, titanium self-aligned silicide, and plasma-enhanced CVD TEOS (tetraethylorthosilicate) as the interlevel dielectric. Circuits fabricated in this technology include a 64 K SRAM.<<ETX>>