William Thomas Cochran

Merged 2.5-V and 3.3-V 0.25-μm CMOS technology

In this paper a merged 2.5 V and 3.3 V high performance 0.25 micrometer CMOS technology is presented. Issues relevant to manufacturing, such as Leff control and the impact of plasma-assisted back-end dielectric depositions on gate oxide reliability and isolation, are discussed. This technology features a 50 angstrom gate oxide, high-energy implant scheme, n+-polysilicon gate, and 4/5 levels of metal. An improvement of 1.45X in circuit performance and 4X in packing density is achieved over our 0.35 micrometer CMOS technology. The nominal ring oscillator delay time is 38(39) ps for 3.3(2.5) V operation.

High contact resistance heavily doped silicided p+ junctions

Submicron CMOS VLSI wafer product yield problems were correlated with a high p+ contact resistance in an Al/TiN/Ti/TiSi2/Si structure. Electrical measurements of contact resistance kelvin (non-interface) versus (interface) contact test structures were used to isolate the high resistance path. Secondary ion mass spectrometry (SIMS) analysis showed good correlation between the Ti to TiSi2 formation and different anneal conditions. The analysis also showed a strong relationship between TiSi2 formation and p+ surface concentration and junction depth. Deeper boron penetration into the silicon will occur with incomplete silicide penetration. The analytical data showed the changes in processing necessary to eliminate the resistance problem and achieve high dopant surface concentration and the desired junction depth.