Morgan J. Thoma

Predictive worst case statistical modeling of 0.8- mu m BICMOS bipolar transistors: a methodology based on process and mixed device/circuit level simulators

The authors discuss the use of mixed-level physics-based device/circuit simulation software and semiconductor process simulator in the construction of predictive worst case process conditions for bipolar transistors currently being manufactured in AT&T 0.8- mu m BICMOS technology. Process fluctuations are introduced into the process simulator using the Latin hypercube (Monte Carlo) sampling method. The method is different from those in previous similar studies in that the compact device model parameter extraction step for each sample process is bypassed and active devices in the circuit are described by the physical device simulator rather than a compact model representation. This eliminates deficiencies associated with compact semiconductor device models. Furthermore, inaccuracies and difficulties introduced by compact model parameter extractions (especially for bipolar transistors) are also eliminated. The method is very useful in identifying critical process steps which determine the electrical performance of the devices and circuits. >

A very high performance and manufacturable 3.3 V 0.35-/spl mu/m CMOS technology for ASICs

In this paper a manufacturable and high performance 0.35 /spl mu/m CMOS ASIC technology optimized for 3.3 V operation is presented. This CMOS technology features a 65 /spl Aring/ gate oxide, single n/sup +/-polysilicon gate, and 3 levels of metal. An improvement of 1.6X in circuit performance and 1.56X in packing density is achieved over AT&Ts previous generation 0.5 /spl mu/m 3.3 volt CMOS technology by device scaling, and aggressive isolation and interconnect design rules. The nominal ring oscillator delay time is 50 ps.

High performance 3.3- and 5-V 0.5-/spl mu/m CMOS technology for ASIC's

Process integration of two manufacturable high performance 0.5-/spl mu/m CMOS technologies, one optimized for 5.0 V operation and the second optimized for 3.3-V operation, will be presented. The paper will emphasize poly-buffered LOGOS (PBL) isolation, MOS transistor design using conventional and statistical modeling to reduce circuit performance sensitivity to process fluctuations, gate oxide and gate length control, and hot carrier reliability of the transistors. Manufacturing and simulation data for both 3.3- and 5.0-V technologies will be shown. The nominal ring oscillator delay is measured for both 3.3- and 5.0-V technologies as 80 ps. Therefore, 5.0-V technology equivalent speed is achieved in the 3.3-V technology with a reduction in power consumption by a factor of 2.4. >

A 0.8-/spl mu/m BiCMOS technology for ASIC applications

A novel process is demonstrated for a 0.8-/spl mu/m BiCMOS process flow by forming a base oxide for NPN transistors using high-pressure oxidation. This process allows improved control over the base implant dose, in the depth of the peak dose, in the precise control of the amount of implant, and in spread of the dose due to thermal processing. Data showing the advantages of this process flow are presented, and some circuit information is given.

High performance 3.3 and 5 volt 0.5-/spl mu/m CMOS technologies for ASICs

Two manufacturable high performance 0.5 pm CMOS technologies, one optimized for 5 V operation and the second optimized for 3.3 V operation, are presented. An improvement of 2 in circuit performance, 3.4 in packing density, 1.5 and 3.2 (for 5 and 3.3 V) in power consumption at constant speed, and 1.45 (for 3.3 V) in power consumption at maximum speed is achieved over AT&Ts previous generation 0.9 /spl mu/m CMOS technology by device scaling, and aggressive interconnect and isolation design rules.<<ETX>>

Plasma Assisted Deposition and Device Technology: Interlevel Dielectric Considerations

In this paper we discuss several approaches for obtaining satisfactory coverage of plasma enhanced CVD TEOS, PETEOS, over severe topography in submicron and larger CMOS technologies. The problems inherent to PETEOS deposition are presented and several solutions are discussed. Adequate film contours can be obtained by the formation of a simple spacer plus a thick film etchback step. Other approaches discussed include a single deposition and etchback, multiple spacer formation, sloped metal profiles, planarization, and profile modification with physical sputtering.

A high-performance submicron CMOS two-level metal technology incorporating a plasma CVD TEOS interlevel dielectric

The process technology for a fifth generation, high-performance, twin-tub, two-level metal, submicron CMOS technology designed for 5-V custom VLSI applications is presented. Features include high-pressure oxidation, lightly doped drain structures for both n and p channel devices, titanium self-aligned silicide, and plasma-enhanced CVD TEOS (tetraethylorthosilicate) as the interlevel dielectric. Circuits fabricated in this technology include a 64 K SRAM.<<ETX>>

Improvements to "A new AC measurement technique to accurately determine MOSFET constants"

Modifications and improvements to the measurement technique described in [1] are presented. In particular, the iterative procedure used to obtain an accurate value for device threshold voltage has been eliminated and replaced by direct calculation. The measurement technique has also been applied to a modulation of the substrate potential in order to obtain an estimate of threshold parameters.