Greg Chrysler

Cooling a Microprocessor Chip

Increasing microprocessor performance has historically been accompanied by increasing power and increasing on-chip power density, both of which present a cooling challenge. In this paper, the historical evolution of power is traced and the impact of power and power density on thermal solution designs is summarized. Industrial and academic researchers have correspondingly increased their focus on elucidating the problem and developing innovative solutions in devices, circuits, architectures, packaging and system level heatsinking. Examples of some of the current packaging and system thermal solutions are provided to illustrate the strategies used in their design. This is followed by a brief discussion of some of the future trends in demand and solution strategies that are being developed by academic and industrial researchers to meet these demands. Potential opportunities and limitations with these strategies are reviewed

Spreading in the heat sink base: phase change systems or solid metals??

Presently, the microelectronics industry needs thermal solutions that are able to dissipate high heat fluxes at low thermal resistance. The majority of original equipment manufacturers (OEMs) within the microelectronics industry would like to achieve this by extending the application of air-cooling technologies since it implies minimal impact to the design of computer systems and is known to be a cost effective solution space. Spreading resistance through the base of the heat sink is one major component of the total thermal resistance from the silicon junction to the local ambient, especially if larger volume heat sinks are to be used. Until now, most of the research has focused on using phase change systems (i.e., vapor chambers) for reducing the spreading resistance of the heat sink base. Since no significant improvements have been achieved, there is a need to determine the envelope of the limitations for phase change-heat spreaders used in processor cooling, and to compare their performance against high thermal conductivity solid metals. Two simple models are presented to address the heat transfer limitations in phase change systems. Using these models, the ratio of phase change spreading resistance over solid metal spreading can be estimated.

Density factor approach to representing impact of die power maps on thermal management

In the microelectronics industry, power has traditionally been the key driver for thermal management. Cooling solutions are typically rated in terms of their power dissipation capacity and efficiency. However, overall power is not the only parameter that affects thermal management. For instance, it is well-known that power density is also important (i.e., it is easier to cool 50 W uniformly distributed on a 20/spl times/20 mm die than the same power on a 10/spl times/10 mm die). Furthermore, even if the die size remains unchanged, nonuniform power distribution at the die level can create localized regions of high power density that require thermal management. This paper proposes a simple metric, density factor (DF/sub jx/), to be used in conjunction with power for quantifying the impact of power density on a given thermal solution. The advantages, limitations, and applicability of this metric are discussed.

Dynamic thermal management using thin-film thermoelectric cooling

Multi-core architectures require Dynamic Thermal Management mechanisms (DTM) to handle (1) multiple hotspots and (2) global chip heating effect while finding the best trade-off between performance and thermal control. In that scenario Thin-Film Thermoelectric Cooling devices can be used to mitigate both effects since they provide on-die localized cooling with a dynamic and heterogeneous effect. This work proposes controlling TFTECs from the microarchitecture for an enhanced Dynamic Thermal Management in multi-core architectures. We show that by using our TFTEC-based proposals the performance is within 8% of that of a thermally-unconstrained processor.

A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model

As CMOS technology scales to nanometer regime, power dissipation issues and associated thermal problems have emerged as critical design concerns in most high-performance integrated circuits (ICs) including microprocessors. In this scenario, accurate estimation of the silicon junction (substrate or die) temperature is crucial for various performance analyses and chip-level thermal management. This paper introduces the notion of self-consistency in the junction temperature estimation by taking into account various electrothermal couplings between chip power, average junction temperature, operating frequency, and supply voltage. The self-consistent solutions of the average junction temperature are shown to have significant implications for various chip-level power, performance, reliability, and cooling cost tradeoffs. Moreover, a realistic package thermal model is introduced that comprehends different packaging layers and noncubic structure of the package, which are not accounted for in traditional analyses. The model is subsequently incorporated in the self-consistent substrate thermal profile estimation, which is discussed in Part II with implications for power estimation and thermal management in nanometer-scale CMOS technologies.

A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management

As transistors continue to evolve along Moores Law and silicon devices take advantage of this evolution to offer increasing performance, there is a critical need to accurately estimate the silicon-substrate (junction or die) thermal gradients and temperature profile for the development and thermal management of future generations of all high-performance integrated circuits (ICs) including microprocessors. This paper presents an accurate chip-level leakage-aware method that self-consistently incorporates various electrothermal couplings between chip power, junction temperature, operating frequency, and supply voltage for substrate thermal profile estimation and also employs a realistic package thermal model that comprehends different packaging layers and noncubic structure of the package, which are not accounted for in traditional analyses. The evaluation using the proposed methodology is efficient and shows excellent agreements with an industrial-quality computational-fluid-dynamics (CFD) based commercial software. Furthermore, the methodology is shown to become increasingly effective with increase in leakage as technology scales. It is shown that considering electrothermal couplings and realistic package thermal model not only improves the accuracy of estimating the heat distribution across the chip but also has significant implications for precise power estimation and thermal management in nanometer-scale CMOS technologies.

Thermal Based Optimization of Functional Block Distributions in a Non-Uniformly Powered Die

Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed has increased and the instruction execution time has decreased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The objective of this paper is to minimize the thermal resistance of the package by optimizing the distribution of the uniformly powered functional blocks. In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a 4 × 4 and 6×6 matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. This analysis has no constraints placed on the redistribution of functional blocks. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. Design guidelines are then suggested regarding the thermal based optimal distribution for any number of functional blocks. The commercial finite element code ANSYS® is used for this analysis.© 2005 ASME

Design optimizations for microprocessors at low temperature

We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refngeration with supply voltage selection, body bias, transistor sizing and shorter channel length. Reducing channel length provides better frequency and power improvement than forward body bias. When, the leakage power is more than 30% of chip power, combining refrigeration with enhancing technology by shorter channel length provides the best trade-off for power and frequency.

Towards a Thermal Moore’s Law

Thermal design power trends and power densities for present and future single-core microprocessors are investigated. These trends are derived based on Moores law and scaling theory. Both active and stand-by power are discussed and accounted for in the calculations. A brief discussion of various leakage power components and their impact on the power density trends is provided. Two different lower limits of heat dissipation for irreversible logic computers that have previously appeared in the literature are discussed. These are based on the irreversibility of logic to represent one bit of information, and on the distribution of electrons to represent a bit. These limits are found to be two or more orders of magnitude lower than present-day microprocessor thermal design power trends. Further, these thermal demand trends are compared to the projected trends for the desktop product sector from the International Technology Roadmap for Semiconductors (ITRS). To evaluate the thermal impact of projected power densities, heat sink thermal resistances are calculated for a given technology target. Based on the heat sink thermal resistance trends, the evolution of a consistent air-cooling limit is predicted. One viable alternative to air-cooling, i.e., the use of high-efficiency solid-state thermoelectric coolers (TECs), is explored in detail. The impact of different parasitics on the thermoelectric figure of merit (ZT) is quantified.

Design rule for minimizing thermal resistance in a non~uniformly powered microprocessor

Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed and the instruction execution time has increased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. Previous work (Kaisare, 2005) has been done to minimize the thermal resistance of the package by optimizing the distribution of the nonuniform powered functional blocks with a specific power matrix. The objective of this paper is to come up with a design rule in general for functional block distribution in a nonuniformly powered microarchitecture. In order to model the nonuniform power dissipation on the silicon chip, the chip surface area is divided into different cases such as 3 times 3, 4 times 4 etc. of power matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements A design rule for minimizing thermal resistance will be developed for any number of functional blocks for a given nonuniformly powered microprocessor. The commercial finite element code ANSYSreg is used for this analysis