Abhijit Kaisare

Thermo-Mechanical Challenges in Stacked Packaging

The convergence of computing and communications dictates building up rather than out. As consumers demand more functionality in their hand-held devices, the need for more memory in a limited space is increasing, and integrating various functions into the same package is becoming more crucial. Over the past few years, die stacking has emerged as a powerful tool for satisfying these challenging integrated circuit (IC) packaging requirements. In this paper, a review of thermo-mechanical challenges for stacked die packaging is discussed.

Thermal management of die stacking architecture that includes memory and logic processor

The convergence of computing and communications dictates building up rather than out. As consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing, and integrating various functions into the same package is becoming more crucial. Over the past few years, die stacking has emerged as a powerful tool for satisfying these challenging integrated circuit (IC) packaging requirements. Previously, present authors reported on the thermal challenges of various die stacking architectures that included memory (volatile and non-volatile) only. In this paper, the focus is on stacking memory and the logic processor on the same substrate. In present technologies, logic processor and memory packages are located side-by-side on the board or they are packaged separately and then stacked on top of each other (package-on-package [PoP]). Mixing memory and logic processor in the same stack has advantage and challenges, but requires the integration ability of economies-of-scale. Geometries needed were generated by using Pro/Engineerreg Wildfiretrade 2.0 as a computer-aided-design (CAD) tool and were transferred to ANSYSreg Workbenchtrade10.0, where meshed analysis was conducted. Package architectures evaluated were rotated stack, staggered stack utilizing redistributed pads, and stacking with spacers, while all other parameters were held constant. The values of these parameters were determined to give a junction temperature of 100degC, which is an unacceptable value due to wafer level electromigration. A discussion is presented in what parameters need to be adjusted in order to meet the required thermal design specification. In that light, a list of solutions consisting of increasing the heat transfer co-efficient on top of the package, the use of underfill, improved thermal conductivity of the PCB, and the use of a copper heat spreader were evaluated. Results were evaluated in the light of market segment requirements

Design for stackability of flash memory devices based on thermal optimization

Convergence of computing and communications dictates building up rather than out. As consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing. Over the past few years, die stacking has emerged as a powerful tool for satisfying challenging IC packaging requirements. As stacked packaging evolves into taller stacks, what issues do we face? Traditionally, chip stacking was carried out with dies of different sizes so the top die was always smaller than the bottom die to permit wire bonding of both. Today, its common to see the stacking of same-size dies or a larger die over a smaller one. One way to accommodate a larger or same-size die on top is to place a spacer (a dummy piece of silicon) between the two. Then, the spacer lifts the top die just enough to allow wire bonding to the bottom die. Another way of stacking same size die is by placing the die in different orientation. This paper focuses on the thermal analysis and optimization of stacked die area array package. Thermal analysis was done on a 3-Die stacked FBGA package using FEM tool ANSYS 9.0. Optimization was then performed on a 3-Die stacked area array package using design explorer. Then the 3-Die stacked package was extended to 7-Die stacked package using ANSYS Workbench 9.0. Three different stack configurations (staggered, rotated and spacer die) with same die size were considered for comparison purposes. Optimization was done by varying seven die powers to get the best design for stackability based on thermal performance of the package.

Thermal Based Optimization of Functional Block Distributions in a Non-Uniformly Powered Die

Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed has increased and the instruction execution time has decreased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. The objective of this paper is to minimize the thermal resistance of the package by optimizing the distribution of the uniformly powered functional blocks. In order to model the non-uniform power dissipation on the silicon chip, the chip surface area is divided into a 4 × 4 and 6×6 matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. This analysis has no constraints placed on the redistribution of functional blocks. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements. Design guidelines are then suggested regarding the thermal based optimal distribution for any number of functional blocks. The commercial finite element code ANSYS® is used for this analysis.© 2005 ASME

A parametric study of a typical high power LED package to enhance overall thermal performance

LED is the revolution in the illumination industry due to its great performance of solid state lighting, environment friendly working, power saving and long lasting life. But dissipation of heat generated and subsequently the thermal management in the LED package is a challenge. A steady state thermal analysis of a typical high power LED model with power dissipation values ranging from 1- 3W, consisting of LED chip, submount, heat slug and silicone enclosure is carried out in order to minimize the junction temperature of LED system. A three dimensional finite element model of the LED package is solved numerically and simulated using ANSYS Workbench to fulfill the purpose. Junction temperature is a critical parameter which affects the efficiency, reliability and lifetime of the LED. In order to minimize the junction temperature, a parametric study is carried out. This study consists of critical geometric parameters such as size of the die, thickness of the submount adhesive, width and thickness of lead frame and height of encapsulation as well as thermal properties of die attach, submount adhesive and encapsulation covering most common adhesive, die attach and encapsulant materials. Recommendations are provided regarding both geometric and process parameters to minimize the junction temperature which will improve the overall reliability and performance of the LED package.

Design rule for minimizing thermal resistance in a non~uniformly powered microprocessor

Microprocessors continue to grow in capabilities, complexity and performance. The current generation of microprocessors integrates functional components such as logic and level two (L2) cache memory into the microprocessor architecture. The functional integration of the microprocessor has resulted in better performance of the microprocessor as the clock speed and the instruction execution time has increased. However, the integration has introduced a layer of complexity to the thermal design and management of microprocessors. As a direct result of function integration, the power map on a microprocessor is highly non-uniform and the assumption of a uniform heat flux across the chip surface is not valid. Previous work (Kaisare, 2005) has been done to minimize the thermal resistance of the package by optimizing the distribution of the nonuniform powered functional blocks with a specific power matrix. The objective of this paper is to come up with a design rule in general for functional block distribution in a nonuniformly powered microarchitecture. In order to model the nonuniform power dissipation on the silicon chip, the chip surface area is divided into different cases such as 3 times 3, 4 times 4 etc. of power matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other was carried out in order to minimize the junction temperature Tj. The best possible Tjmax reduction could thus be found. In reality (and at a later date) constraints must be placed regarding the maximum separation of any 2 (or more) functional blocks to satisfy electrical timing and compute performance requirements A design rule for minimizing thermal resistance will be developed for any number of functional blocks for a given nonuniformly powered microprocessor. The commercial finite element code ANSYSreg is used for this analysis

Development of an Analytical Model to a Temperature Distribution of First Level Package With a Non-Uniformly Powered Die

Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. Previous work has been done which includes numerical analysis and thermal Based optimization of a typical package consisting of a non-uniformly powered die, heat spreader, TIM I &II and the base of the heat sink. In this paper, an analytical approach to temperature distribution of a first level package with a non-uniformly powered die is carried out for the first time. The analytical model for two layer bodies developed by Haji-Sheikh et al. is extended to this typical package which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology will be applied to solve the equations for various surfaces to calculate maximum junction temperature for given multilayer body. Finally validation of the analytical solution will be carried out using developed numerical model.Copyright

Optimal thermal characterization of a stacked die package with TSV technology

Through silicon via (TSV) technology is one of the most rapidly developing technologies in the semiconductor industries and assures the development for the continued role of Moores law and multichip integration as well as packaging approaches. Wire bond and flip-chip have been in use for long time now while TSV is the latest technology of 3D integration system which is used for primary interconnection. The benefits of the use of TSV technology are increased performance, reduced form factor, cost reduction of the package etc. A steady state thermal analysis is carried out of a stacked die package using through silicon vias technology to minimize maximum junction temperature for the various set of geometric and process parameters. A three dimensional finite element model (octant model) of a stacked package that consists of stacked dice, solder interconnect substrate, underfill, through silicon vias and PWB is solved numerically to minimize the junction temperature of the stacked package. A parametric study consists of critical geometric and process parameters such as aspect ratio (configuration of vias structure), underfill thickness, underfill thermal conductivity and convection heat transfer coefficient (h) applied on the top of mold cap. Recommendations are provided regarding the development of design guidelines for through silicon vias structure which can have impact on geometric as well as material configuration in keeping junction temperature within limit.

Thermo-mechanical analysis of a typical solar module: A parametric study

Photovoltaic power is emerging as a major power resource, steadily becoming more affordable and proving to be more reliable than utilities. The photovoltaic effect is the basic principal process by which a photovoltaic (PV) cell converts sunlight into DC electricity. PV cells were developed as a spin-off of transistor technology. Photovoltaic modules are interconnected assemblies of photovoltaic cells (solar cells) packaged in a weather tight housing. The module is encapsulated with tempered glass on the front surface, and with a protective and waterproof material on the back surface. The edges are sealed for weatherproofing as photovoltaic modules have to withstand a number of environmental influences like irradiance, temperature, mechanical stresses, atmosphere, humidity, moisture in their long life time. It is very important to understand the mechanical stability of theses solar panels as they undergo various loading and environmental conditions such as thermo-mechanical loading, thermal cycling, wind loading, effect of hell storm etc. A three dimensional finite element model of a typical solar module assembly that consists of silicon cells and bus bars sandwiched between glass cover and backsheet using an EVA and adhesive is solved numerically to study the impact of stresses induced on mechanical integrity of the silicon and bus bar during cool down of the solar assembly. In this analysis, a stress free temperature of 60° C, while temperature range of -40° C to 120° C is applied to the module and stresses are calculated at the Si, bus bars, adhesive, solder pads and glass to assess the reliability of the overall package. A parametric study of critical geometric parameters such as Si, bus bar, adhesive and glass thickness as well as mechanical material properties (E and a) of adhesive is carried out to minimize the maximum stresses on the overall module. Recommendations are provided to minimize the overall stresses which eventually results in a productive design and installation of a solar module assembly.

Design for Reliability of Stacked Die Package Using TSV Technology

A thermo-mechanical analysis is carried out on a stacked die package having through silicon via technology to study the overall reliability of the package due to varying aspect ratio (size and shape) of through silicon vias, silicon die thickness, underfill thickness and underfill material properties. Through silicon via technology is one of the most rapidly developing technologies in the semiconductor industry and assures the development for the continued role of Moore’s law and multichip integration as well as packaging approaches. Wire bond and flip-chip have been in use for long time now while TSV is the latest technology of 3D integration system which is used for primary interconnection. The benefits of the use of TSV technology are increased performance, reduced form factor and cost reduction of the package. A three dimensional finite element model of a stacked package that consists of stacked dice using through silicon vias, solder interconnect, underfill, substrate and PWB is solved numerically to assess the reliability of the overall stacked package. In this analysis, stress free temperature for stacked package is kept at 125°C while room temperature is 25°C to carry out the simulation of the stresses post cure cool down of the stacked package. Stresses are calculated at the die as well as interfaces between underfill and die and underfill and substrate to assess the reliability of the overall package. A parametric study of critical geometric parameters such as aspect ratio, thickness of silicon die and underfill thickness and process parameters is carried out to minimize the maximum stresses on the overall stacked package. Recommendations are provided with respect to controlling the critical parameters such as aspect ratio, silicon thickness, underfill thickness and varying the underfill material properties (E and α) to improve the overall reliability and strength of the package.Copyright