Chia-Pin Chiu

Key challenges for the piezo technology with applications to low form factor thermal solutions

The thermal performance of piezoelectric actuators for cooling in low form factor applications is presented. A significant reduction in thermal resistance is achievable when compared to the baseline natural convection. Comparisons with fans and blowers of similar size result in comparable performance but at greatly reduced power consumption

Thermal Management of a Stacked-Die Package in a Handheld Electronic Device Using Passive Solutions

Various passive thermal management schemes are discussed for a high power component in a handheld electronic device. The validated package and system thermal model based on JEDEC standards and a cell phone mock-up testing were used for the extensive analysis. Also the empirical data was collected to validate thermal improvement predicted by computational fluid dynamics analysis. By using the validated thermal model, the design cycle and time-to-market can be significantly reduced.

Experimental method of measuring C4 die bump temperature for electronics packaging

Recent trends in the semiconductor industry are driving a continuous increase in power dissipation, but require a lighter, more compact and thinner packaging technology. One of the concern areas is the increasing temperature of the C4 die bump. As the power continues to increase, the electrical current through the C4 die bump increases accordingly, resulting in increased bump temperature due to Joule self-heating and trace heating. This increased electrical current and temperature causes electro-migration failure of the C4 die bumps. In order to fully understand and avoid this failure phenomenon, we need to know the C4 die bump temperature. This has necessitated the development of a measurement method for the C4 die bump temperature. This paper discusses the methodology of measuring the C4 die bump temperature as well as results of our measurements. The experimental study includes variation of the bump current, the die power dissipation, and different enabling thermal solutions including natural convection and forced convection conditions. The experimental results show the effect of the Joule self-heating of the bump, the effect of the trace heating to the bump, the effect of the die heating and the effect of the bump and trace resistivity.

Thermal management of a stacked-die package in a handheld electronic device using passive solutions

Various passive thermal management schemes are discussed for a high power component in a handheld electronic device. The validated package and system thermal model based on JEDEC standards and a cell phone mock-up testing were used for the extensive analysis. Also the empirical data was collected to validate thermal improvement predicted by computational fluid dynamics analysis. By using the validated thermal model, the design cycle and time-to-market can be significantly reduced.

Optimization of packaging materials and design for thermal management in stacked-die packages

Various package level thermal management schemes are discussed. Extensive sensitivity study data of thermally conductive packaging materials such as die adhesive, mold compound, and board level underfill are reviewed on different package architectures by using JEDEC standards. Thermal benefits of heat spreader embedded stacked-die packages are also investigated. By using the validated detailed package thermal model, the design cycle and time-to-market can be significantly reduced