Greg Costrini

Dual stress liner enhancement in hybrid orientation technology

Hybrid orientation technology (HOT) has been successfully integrated with a dual stress liner (DSL) process to demonstrate outstanding PFET device characteristics in epitaxially grown [110] bulk silicon. Stress induced by the nitride MOL liners results in mobility enhancement that depends on the designed orientation of the gate, in agreement with theory. Compressive stressed liner films are utilized to increase HOT PFET saturation current to 635 uA/um I/sub DSat/ at 100 nA/um I/sub OFF/ for V/sub DD/=1.0 V at a 45 nm gate length. The AC performance of a HOT ring oscillator shows 14% benefit from [110] silicon and an additional 8% benefit due to the compressive MOL film.

Investigation of CMOS devices with embedded SiGe source/drain on hybrid orientation substrates

CMOS devices with embedded SiGe source/drain for pFETs and tensile stressed liner for nFETs have been demonstrated for the first time on hybrid orientation substrates. Ring oscillators have also been fabricated. Significant performance improvement is observed in hybrid orientation substrates compared to (100) control substrates with embedded SiGe.

A 0.18 /spl mu/m logic-based MRAM technology for high performance nonvolatile memory applications

This paper discusses the fabrication of a 2 Kb array test chip with a 1.66 /spl mu/m/sup 2/ cell and a corresponding 128 Kb MRAM (Magnetoresistive Random Access Memory) with a 1.4 /spl mu/m/sup 2/ cell. The technology features a 1 transistor 1 MTJ (Magnetic Tunnel Junction) cell in a 0.18 /spl mu/m, 3 level Cu metallization logic-based process. Outlined here is a yield analysis of the read operation, which is governed by the MTJ resistance distribution function and a systematic study of the write operation. MRAM functionality, with a checkerboard disturb pattern, was obtained after process optimization. Write endurance tests did not show degradation of the cell properties.

Addressable Arrays Implemented with One Metal Level for MOSFET and Resistor Variability Characterization

Addressable array test structures for rapid collection of statistical distributions of MOSFET parameters and parasitic resistances are described. A unique feature of these designs is that they require only one level of metal, yet are compact for placement in the scribe line for early process learning. MOSFET measurements are made over full range of I-V characteristics including leakage currents of individual devices in the sub-threshold region. A modular approach for test structure integration and parallel testability enables high efficiency in design and data acquisition.

Three dimensional (BA, SR) TIO3 stack capacitors for dram application

Abstract Three dimensional integration of BSTO thin films for Gigabit DRAM application is performed by a MOCVD BST process combined with a high temperature barrier stack of TaSiN/Ir/IrO2 with SiO2 sidewall protection. The SiO2 layer is formed by a new low temperature HDP process. This barrier stack enables the use of a new two step high temperature MOCVD BST process, which results in high quality BST films. First, a very thin BST seed layer is deposited at 450°C. The second layer is formed at 640°C. Using these two key processes, we have established a baseline for BST capacitors on 0.2μm feature size. 256k capacitor arrays show capacitance up to 18.1 fF/cell with excellent leakage current around 1 fA/cell (DC, 1V). The capacitance is scaling with different capacitor arrays (4k to 256k).

Electrodes and Barriers for Dram and Feram: Processing, Integration, and Fundamentals

Materials requirements for electrodes and barriers in high density dynamic random access memory (DRAM) and ferroelectric random access memory (FERAM) are reviewed, and some approaches to barrier materials and device geometries are described. Electrode/barrier topics covered in more detail include Pt reactivity with Si-containing barriers and dielectric overlayers, the application of a Bragg-Brentano x-ray diffraction technique to quantitatively probe Pt and Ir electrode morphology and thickness changes during ferroelectric processing, the stability of metal oxide electrode materials in reducing ambients, electrode patterning techniques (including Pt electroplating), and electrical properties of 3-D capacitors in 256k arrays as a function of top electrode annealing treatments.