Gregory N. Heiler

Effect of SiO 2 and SiO 2 /SiN x Passivation on the Stability of Amorphous Indium-Gallium Zinc-Oxide Thin-Film Transistors Under High Humidity

We studied the environmental stability of amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) with single-layer (SiO2) and bilayer (SiO2/SiNx) passivation under high-humidity (80%) storage. During the 30 days of investigation, all single-layer passivated TFTs showed negative turn-ON voltage shifts (AVON), the size of which increased with storing time. The negative A VON is attributed to donor generation inside the active a-IGZO caused by the diffusion of ambient hydrogen/water molecules passing through the SiO2 passivation layer. The X-ray photoelectron spectroscopy depth profile for the SiO2 passivated structures confirms that the concentration of oxygen vacancies, which is initially larger at the a-IGZO/SiO2 interface, compared with the bulk a-IGZO, decreases after 30 days of storage under high humidity. This can be explained as the passivation of oxygen vacancies by diffused hydrogen. On the other hand, all bilayer passivated TFTs showed good air stability at room temperature and high humidity (80%).

Infinite Output Resistance of Corbino Thin-Film Transistors With an Amorphous-InGaZnO Active Layer for Large-Area AMOLED Displays

We report a low-voltage-driven amorphous indium-gallium-zinc oxide (a-IGZO) semiconductor-based Corbino (circular) thin-film transistor (TFT) with infinite output resistance beyond pinchoff. The Corbino TFT has inner and outer concentric ring electrodes, and when the latter is the drain, channel width (W) decreases with channel length (L), such that the W/L ratio is not changed after pinchoff. As demonstrated herein, this a-IGZO Corbino TFT is, therefore, a good candidate for uniform current drivers in applications, such as active-matrix organic light-emitting diode display pixels, where it would maintain the same drive (diode) currents, even with variations in supply voltage (VDD).

Analysis of Improved Performance Under Negative Bias Illumination Stress of Dual Gate Driving a-IGZO TFT by TCAD Simulation

We report the numerical simulation of the effect of a dual gate (DG) TFT structure operating under dual gate driving on improving negative bias illumination stress (NBIS) of amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs). With respect to the transfer characteristics of a-IGZO TFTs, we show a larger negative threshold voltage shift (ΔVTH) with increasing a-IGZO active layer thickness. This trend is confirmed by TCAD simulation, where the initial transfer curve is plotted under varying a-IGZO thickness keeping a constant density of states. Under varying a-IGZO thickness, TCAD simulation results confirm TFTs under DG driving shows significantly less ΔVTH shift under NBIS compared with that of single gate (SG) driving TFTs. Under 10 K seconds of NBIS, TCAD simulation results show the increase in donor-like states (NGD) by 5.25 × 1017 cm-3 eV-1 and acceptor-like states (NGA) by 7.5 × 1016 cm-3 eV-1.

Intrinsic Channel Mobility of Amorphous, In–Ga–Zn–O Thin-Film Transistors by a Gated Four-Probe Method

Intrinsic mobility and intrinsic channel resistance (R_CH) of amorphous, In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) with varying channel length (L) are investigated using a gated four-probe back-channel-etched TFT design. The intrinsic R_CH is found to decrease from ~500 to ~250 kΩ per unit area by increasing V_GS from 10 to 20 V. The intrinsic mobility is ~17 cm²/V·s, which is about 20% higher than that derived from the normal two-point probe measurements. Source and drain parasitic resistance (R_PAR) of the a-IGZO TFTs is found to be of the same order of magnitude as the R_CH-which is different from hydrogenated amorphous-silicon (a-Si:H) TFTs, where TFT operation is dominated by R_PAR.

Optimization of the a -SiC p -layer in a -Si:H-based n-i-p Photodiodes

Our work is aimed at enhancing the external quantum efficiency (EQE) of n-i-p photodiodes by reducing the absorption losses in the p-layer and the recombination losses in the p-i interface. We have applied boron-doped and undoped hydrogenated amorphous silicon carbon alloy (a-SiC:H) grown in hydrogen-diluted, silane-methane plasma to both the p-layer and undoped buffer layer, thus tailoring the p-i interface. The current-voltage, capacitance-voltage, and spectral-response characteristics of fabricated photodiodes are correlated with the doping level, optical band gap, and deposition conditions for a-SiC:H layers. The optimized device exhibits a leakage current of about 110 pA/cm2 at the reverse bias of 5 V, and a peak value of 89% EQE at a wavelength of 530 nm. At shorter wavelengths, the EQE decreases down to 56% at a 400 nm wavelength. Calculations of transmission/reflection losses at the front of the photodiode show that observed short-wavelength sensitivity enhancement can be attributed to improved separation of electron-hole pairs in the p-layer depletion region.

Transient current in a-Si:H-based MIS photosensors

Large-area amorphous silicon (a-Si:H) sensor arrays are widely used for medical x-ray imaging, nondestructive testing and security screening. Most of the commercially available detectors are of the indirect conversion type, in which an x-ray phosphor screen is optically coupled to an array of a-Si:H sensors. The a-Si:H PIN photodiode and the MIS photoelectric converter are two alternative sensing elements used in these detectors. The major advantage of the MIS structure over PIN is fact that this device has the same layer sequence as the a Si:H TFT switch and therefore, they can be fabricated simultaneously resulting in an effective reduction in the lithography mask count. The main disadvantage of the MIS structure is the higher noise level due to transient dark current. The transient dark current originates from traps at the semiconductor-insulator interface and i-layer bulk defects. In this work we analyze the transient current transport in segmented-gate/SiN/a Si:H/n+/ITO structures under different biasing conditions and temperatures. Using a home-made setup the dark current decay was measured within an interval of 1 second in the temperature range from 294 to 353K. It is found that the dark current component associated with charge trapping at the insulator-semiconductor interface can be largely eliminated by adjusting the bias voltage during the refresh period. Under optimized biasing conditions and elevated temperatures the bulk current component becomes dominant.

High Performance Hydrogenated Amorphous Silicon n-i-p Photo-diodes on Glass and Plastic Substrates by Low-temperature Fabrication Process

We report on the fabrication and characterization of hydrogenated amorphous silicon (a-Si:H) films and n-i-p photodiodes on glass and PEN plastic substrates using low-temperature (150°C) plasma-enhanced chemical vapor deposition. Process conditions were optimized for the i-a-Si:H material which had a band gap of ~1.73 eV and low density of states (of the order 10 15 cm -3 ). Diodes with 0.5 μm i-layer demonstrate quantum efficiency ~70%. The reverse dark current of the diodes on glass and PEN plastic substrate is ~10-11 and below 10 -10 A/cm 2 , respectively. We discuss the difference in electrical characteristics of n-i-p diodes on glass and PEN in terms of bulk- and interface-state generation currents.

Optimization of p-type nanocrystalline silicon thin films for solar cells and photodiodes

We report on structural, electronic, and optical properties of boron-doped, hydrogenated nanocrystalline silicon (nc-Si:H) thin films deposited by plasma-enhanced chemical vapor deposition (PECVD) at a substrate temperature of 150°C Film properties were studied as a function of trimethylboron-to-silane ratio and film thickness. The film thickness was varied in the range from 14 to 100 nm. The conductivity of 60 nm thick films reached a peak value of 0.07 S/cm at a doping ratio of 1%. As a result of amorphization of the film structure, which was indicated by Raman spectra measurements, any further increase in doping reduced conductivity. We also observed an abrupt increase in conductivity with increasing film thickness ascribed to a percolation cluster composed of silicon nanocrystallites. The absorption loss of 25% at a wavelength of 400 nm was measured for the films with optimized conductivity deposited on glass and glass/ZnO:Al substrates. A low-leakage, blue-enhanced p-i-n photodiode with an nc-Si p-layer was also fabricated and characterized.

Temperature dependence of leakage current in segmented a-Si:H n-i-p photodiodes

Hydrogenated amorphous silicon (a-Si:H) n-i-p photodiodes may be used as the pixel sensor element in large-area array imagers for medical diagnostics applications. The dark current level is an important parameter that dictates the performances of these types of pixelated imaging devices. Through measurements performed at different ambient temperatures, the leakage current components of segmented a-Si:H n-i-p photodiodes were extracted and analyzed. It was found that the central component of the reverse current depends exponentially on bias and temperature. The activation energy of this component is independent of bias. The peripheral component of reverse current exhibits linear bias dependence at temperatures up to 50°C, while the contribution of this component diminishes at high temperatures. The dependence of dark current components on bias and temperature could be described by compact analytical equations. The model of forward and reverse dark current characteristics in temperature range was implemented in Verilog-A hardware description language.

Physically Based Compact Model for Segmented a-Si:H n-i-p Photodiodes

Hydrogenated amorphous silicon (a–Si:H) n–i–p photodiodes are used as pixel sensor elements in large-area flat-panel detectors for medical imaging diagnostics. Accurate model of the sensor plays an imperative role in determining the performances of the detector systems as well as ascertaining design issues prior to production. This work presents the formulation of a compact model for segmented a–Si:H n–i–p photodiodes suitable for circuit-level simulation. The underlining equations of the model are based on device physics where the parameters are extracted from pertinent measurement results of previously fabricated a–Si:H n–i–p photodiodes. Furthermore, the implemented model allows photoresponse simulation with the addition of an external current source. Results of the simulation demonstrated excellent matching with measurement data for different photodiode sizes at various temperatures. The model is implemented in Verilog-A and simulated under Cadence Virtuoso design environment using device geometry and extracted parameters as inputs. The model formulation and parameter extraction process, as well as measurements and simulation results are presented.