Gregory Riou

Recent developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking

This paper will focus on recent results of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. We report on bonding quality, wafer-to-wafer alignment accuracy and electrical connectivity. Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers. A particular concern is related to the planarization (e.g. CMP) of Cu-SiO2 hybrid surfaces: copper dishing and erosion need to be minimized in order to obtain high bonding quality. The bonding quality is assessed by the evaluation of bonding strength, interfacial defects, wafer-to-wafer misalignment and electrical contact resistance at the Cu-Cu interface. The bonding strength evolution with post-bond annealing is reported and discussed for the case of patterned surfaces. Scanning Acoustic Microscopy (SAM) imaging of bonding interface is performed to monitor bonded defects. Process conditions have been optimized to minimize the post bond annealing (thermal budget) at temperatures below 400°C.

Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment

In this paper the integration challenges related to oxide-oxide bonding for wafer-to-wafer stacking technology are discussed. Furthermore, interface defectivity, wafer-to-wafer alignment and bond strength data are presented.

Metrology Challenges for the Ultra‐thin SOI

Future generations of CMOS technology require aggressive scaling of SOI and BOX layer thickness. This will pose significant challenges for SOI specific metrology. Future requirements for layer thickness measurements, LPD inspection, electrical and structural characterization of SOI stack are discussed. Possible directions for future development of appropriate techniques are proposed.

Advanced Metrologies for Topography and Thickness Measurements

Despite its limitations, like the low through put, Atomic force microscopy (AFM) is in common use in the semiconductor industry for surface geometry characterization. Recent development in optical profilometry, Index Corrected Topography (ICT), further expands the technique by analysis of the collected interferograms to extract films parameters (thickness, for instance) and surface topography. This model based technique delivers literally complete information (e.g. topography, roughness, filmstack properties) of measured structure with sub‐micron lateral resolution and angstrom vertical resolution. The approach is a strong asset since it allows contact less topography measurement of wafer surfaces.In this paper we will show how this specific metrology can meet the aforementioned stringent requirements. The comparison with both the AFM and the spectroscopic ellipsometry will be presented.