Mariam Sadaka

Recent developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking

This paper will focus on recent results of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. We report on bonding quality, wafer-to-wafer alignment accuracy and electrical connectivity. Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers. A particular concern is related to the planarization (e.g. CMP) of Cu-SiO2 hybrid surfaces: copper dishing and erosion need to be minimized in order to obtain high bonding quality. The bonding quality is assessed by the evaluation of bonding strength, interfacial defects, wafer-to-wafer misalignment and electrical contact resistance at the Cu-Cu interface. The bonding strength evolution with post-bond annealing is reported and discussed for the case of patterned surfaces. Scanning Acoustic Microscopy (SAM) imaging of bonding interface is performed to monitor bonded defects. Process conditions have been optimized to minimize the post bond annealing (thermal budget) at temperatures below 400°C.

Direct bonding for wafer level 3D integration

3D integration is a promising and fast growing field that addresses the convergence of Moores Law and more than Moore. 3D integration offers higher performance, higher density, higher functionality, smaller form factor, and potential cost reduction. With this emerging field, new and improved technologies will be necessary to meet the associated manufacturing challenges. This paper describes some 3D building blocks describing oxide to oxide and metal to metal bonding with alignment

Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment

In this paper the integration challenges related to oxide-oxide bonding for wafer-to-wafer stacking technology are discussed. Furthermore, interface defectivity, wafer-to-wafer alignment and bond strength data are presented.

3D integration: Advantages, enabling technologies & applications

The microelectronic industry has arrived at a crossroads. There is the challenge of continued Moores Law scaling and the ever-growing consumer demand for smaller, faster electronics with extended and new functionalities. 3D integration is a promising and fast-growing field that addresses the convergence of Moores Law and more than Moore. 3D integration offers a path for higher performance, higher density, higher functionality, smaller form factor, and potential cost reduction. Through this emerging field, new and improved technologies and integration schemes will be necessary to meet the associated manufacturing challenges; this paper describes the advantages of 3D integration, enabling technologies & the driver applications.

Smart stacking TM technology: An industrial solution for 3D layer stacking

Smart Stacking™ is a wafer-to-wafer stacking technology of partially or fully processed wafers. This technology enables transferring very thin layers in a high volume manufacturing environment. The core technologies are surface conditioning, low temperature direct bonding and wafer thinning (figure 1). This technology is adapted for advanced semiconductor applications such as Back Side Illumination (BSI) CMOS Image Sensors (CIS) as well as 3D integration approaches [1,2].

Smart Stacking™ and Smart Cut™ technologies for wafer level 3D integration

The wafer stacking technology for 3D integration requires high quality bonding interfaces with uniform bonding films. Two wafer level stacking technologies - Smart Stacking™ and Smart Cut™ - are developed to address the manufacturing challenges for improved process cost efficiency.