Gu-Sung Kim

The electrical, mechanical properties of through-silicon-via insulation layer for 3D ICs

This paper descibes variety of methods to examine the electrical and physical characteristics of the isolation layer deposited on TSV(Through-Si-Via). A sample was manufactured for the experiment with a diameter of 10μm and a depth of 50μm using Deep-RIE(Reactive Ion Etching). SiO2 thin-film was deposited on the TSV sample by two separate procedures: PECVD (Plasma Enhanced Chemical Vapor Deposition) and PETEOS (PE Tetra-Ethyl-Ortho-Silicate). The insulating layer of TSV is supposed to decrease inter-diffusion between materials that fill the wall and its interior, improve adhesion and prevent electrical leakage. Hence, physical deposition characteristics, such as the surface step coverage, deposition rate, and films density were observed and analyzed in order to determine if the deposited layer met the above criteria. The results confirmed that the thin layer deposited by PETEOS deposition was superior to that formed by PECVD in every category considered. Moreover, in order to assess the electrical characteristics, the interior of via hole was filled with copper (Cu) using the damascene process to create a sample. I-V was measured using the Time Dependent Dielectric Breakdown (TDDB) method for the sample, The measurement values were used to check the voltage level where the leakage current appeared. These experiment results indicate that the failure rate of the insulating layer depends upon the films thickness and the deposition process. This assertion provides clues for conjecturing the main causes of insulation destruction. In this study, we determined the best deposition process for insulating the interior of TSV and the optimal insulating layer thickness in relation to the usage voltage.

A warpage of wafer level bonding for CIS (CMOS Image Sensor) device using polymer adhesive

The polymer adhesive bonding technology using wafer-level technology was investigated to adhere silicon to glass wafer and it analyzed warpage caused in cemented wafer and the degree of intensity. We executed the wafer adhesion depending on temperature (130°C, 190°C), the pressure (5000N, 8000N), the height of the adhesive layer (10μm, 20μm) and the adhesive time (process time, the time for temperature rising) of each of the silicon and glass wafer. The warpage was measured using three-dimensional measuring equipment and the results were caused by the differences of CTE and the physical stress. It was also confirmed that the more the temperature of Si wafer, adhesive pressure and adhesive layer was lowered in order to improve the warpage results, the more warpage decreased, and that the adhesive time and temperature differences of glass wafer were relatively insufficient factors. To judge the degree of wafer adhesion, the shear intensity was tested and it showed that the higher the adhesive temperature of glass wafer was, the more degree of shear intensity it showed, and that the other conditions showed little effects. Also, in the center of the adhesive wafer where the warpage occurred showed that the more it was getting to the edge, the more shear intensity decreased, and that the stress related with the occurrence of warpage also had effects on the state of adhesion.

A study of ultrasonic bonding flip chip process and its reliability for low temperature interconnection

The purpose of studying is to confirm the reliability criteria of ultrasonic bonding with different chip size. To ensure this purpose, three kinds of specimens are prepared for compared evaluation, and bonding condition is secured by reliability assessment. For testing, chips are created with 5 mm × 5 mm, 10mm × 10mm, and 15mm × 15mm. The bond interconnections between chip and substrate are designed more than fifteen points with different daisy chain. Substrates called PCBs also prepared to fit each chip. The ultrasonic bonding process is progressed to use the anisotropic conductive films (ACF). For comparing the bonding process, all specimens also progressed using thermo-compression bonding.

A method to produce printed circuit boards with embedded semiconductors using stress buffer layers

In the case of embedded chip type CSPs (Chip Scale Packages) made by embedding chips in PCBs (Printed Circuit Boards), problems occur due to differences in the CTE (Coefficient of Thermal Expansion) between the PCBs and the chips. This study tested a method to solve this problem by inserting thermal SBLs (Stress Absorbing Layers) into the embedded chips, thereby improving the reliability of the connection between the chip and the PCB. This study focused on a production method used to form a SBL on a Silicon Active Layer in order to make embedded PCBs and the material used as SBLs was absorbent in the polyimide family, which was composed of a material containing at least 30% polysiloxanes. For the experiment, two types of samples were used, including: 20mm × 20mm sized silicon active layers without any SBL formed on them; those with an SBL formed only on the top surface. The samples were produced and placed on the PCBs. To examine the effects of the physical damage, 3 point bending tests were conducted and the results were analyzed.