Guangyi Lu

Comprehensive study and corresponding improvements on the ESD robustness of different nLDMOS devices

Four-terminal and three-terminal asymmetrical n-type LDMOS (asym-nLDMOS) devices are investigated in 0.18μm 40V SOI BCD technology. To improve normal asym-nLDMOS devices ESD robustness, an additional p-sink implant is added beneath their source/drain diffusion regions. Transmission line pulse measured results show that the novel asym-nLDMOS devices have a suitable triggering voltage and 30-48% improvement of second breakdown current.

A power clamp circuit using current mirror for on-chip ESD protection

A power clamp circuit using current mirror is proposed in this article. The current mirror is used for capacitance multiplication in the proposed circuit. Besides, the proposed circuit has different turn-on and turn-off paths towards clamp transistor and it employs a non-traditional phase inverter in the turn-on path of clamp transistor. Simulation results verify that the proposed circuit has enhanced ability to discharge static charges during an ESD event while making the ESD pulse detection CR time constant notably smaller. With the reduction of CR time constant, the proposed circuit has better immunity to mis-triggering and is less chip area-consuming.

A novel ESD self-protecting symmetric nLDMOS for 60V SOI BCD process

A novel symmetric n-type lateral diffusion MOS (sym-nLDMOS) is presented. Fabricated without any extra mask in a standard 0.18 μm 60 V SOI BCD process, the new sym-nLDMOS has an ability of electrostatic discharge (ESD) self-protection. The TLP measured results show about 1X improvement of It2 in the novel sym-nLDMOS. The output characteristics of the novel device are also be measured.

A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications

This work presents a novel power-rail electrostatic discharge (ESD) clamp circuit for nanoscale applications. By skillfully incorporating transient and static ESD detection mechanisms into its detection circuit, the proposed circuit achieves a wide range of adjustable triggering voltage (Ft1) while maintaining low standby leakage current (Ileak). Besides, the proposed circuit achieves significantly-improved false-triggering immunity compared with the transient-triggered circuit. All investigated circuits are fabricated in a 65-nm CMOS process. Simulation and test results have both confirmed the superiority of the proposed circuit. In addition, the proposed circuit achieves similar triggering behaviors in both transmission line pulsing (TLP) and very fast TLP (VF-TLP) tests.

Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling

Gate-grounded NMOS (ggNMOS) transistors have widely served as electro-static discharge (ESD) protection devices for integrated circuits. The layout strategy of ggNMOS greatly influences its ESD protection characteristics. Layout strategies forvariation of the number of substrate-pickup stripes are investigated in this paper. Direct current and transmission-line pulsing test results are presented to verify that adjustable holding voltages are accessed by variation of the number of substrate-pickup stripes. The design with two evenly distributed substrate-pickup stripes among different fingers is found to exhibit the highest second break current and optimal width-scaling characteristics.

Transient and Static Hybrid-Triggered Active Clamp Design for Power-Rail ESD Protection

A transient and static hybrid-triggered active clamp is proposed in this paper. By skillfully incorporating different detection mechanisms, the proposed clamp achieves enhanced static electrical overstress protection capability over the transient one. Furthermore, the proposed clamp achieves improved electrostatic discharge reaction speed in both human body model and charged device model events over the static one. Moreover, the superior transient-noise immunity of the proposed clamp over traditional transient ones is essentially revealed in this paper. The proposed clamp is successfully verified in a 65-nm bulk CMOS process. In addition, the design flexibility of the proposed clamp for other processes is also deeply discussed in this paper.

A wafer-level characterization method of ESD protection circuits for both component-level and system-level applications

Electrostatic discharge (ESD) protection circuits are often designed with detection circuits to trigger clamp devices to bypass ESD currents. In order to fully characterize performance of these protection circuits, a wafer-level characterization method is proposed in this work. By separating the detection rail from the supply rail, triggering actions resulted from detection circuits can be clearly captured by the proposed method. Besides, both the component-level triggering criteria and system-level transient-induced latch-up (TLU) immunity of ESD protection circuits can be fully characterized by the proposed method. Silicon-data based case studies are presented in this work to verify the validity of the proposed method.

Novel insights into the power-off and power-on transient performance of power-rail ESD clamp circuit

Based on the thorough characterization of the transient performance of a power-rail ESD clamp circuit, novel insights concerning the bigFET response time, power-off triggering criteria and power-on noise immunity with respect to the disturbance waveform are clearly summarized in this work. The instructive qualities of these insights are deeply discussed.

A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network

A novel power-rail ESD clamp circuit with a small time constant to achieve a longer turn-on time is proposed. During an ESD event, the turn-on time of discharge transistor Mbig in the proposed circuit is 5.87 times of that of the traditional one; under the normal power supply condition, the total leakage current has reduced to 4.635% compared with the leakage current of traditional circuit; under fast power supply condition, the proposed power-rail ESD clamp circuit can work efficiently with a turned off discharge transistor, thus avoiding the loss of power consumption due to the false triggering in traditional power-rail ESD clamp circuit.

Analysis of dummy-gate dual-directional SCR (dSCR) device for ESD protection

A novel dual-directional silicon controlled rectifier (dSCR) device with dummy gate for electrostatic discharge (ESD) protection is presented. Compared with the traditional dSCR, the novel device has the desirable characteristics of dual-directional conduction, a low ESD trigger voltage, an adjustable ESD holding voltage and non-consumption of the extra area.