Ganggang Zhang

Multiregion DCIV: A Sensitive Tool for Characterizing the

By measuring the substrate current under the forward bias of source/drain-substrate junction, a multiregion direct current current-voltage (MR-DCIV) technique is used to characterize the interface trap density and location in shallow-trench-isolation (STI)-based laterally diffused metal-oxide-semiconductor devices. The interface traps in LDMOSFETs yielded sharp well-resolved peaks in MR-DCIV current spectra. The interface traps in STI region can be measured without inducing any potential damages on the gate oxide by this nondestructive characterization tool. This technique can provide not only across-wafer as-grown interface trap profile but also stress-induced defect information.

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A power clamp circuit using current mirror is proposed in this article. The current mirror is used for capacitance multiplication in the proposed circuit. Besides, the proposed circuit has different turn-on and turn-off paths towards clamp transistor and it employs a non-traditional phase inverter in the turn-on path of clamp transistor. Simulation results verify that the proposed circuit has enhanced ability to discharge static charges during an ESD event while making the ESD pulse detection CR time constant notably smaller. With the reduction of CR time constant, the proposed circuit has better immunity to mis-triggering and is less chip area-consuming.

Interfaces in LDMOSFETs

A novel symmetric n-type lateral diffusion MOS (sym-nLDMOS) is presented. Fabricated without any extra mask in a standard 0.18 μm 60 V SOI BCD process, the new sym-nLDMOS has an ability of electrostatic discharge (ESD) self-protection. The TLP measured results show about 1X improvement of It2 in the novel sym-nLDMOS. The output characteristics of the novel device are also be measured.

A power clamp circuit using current mirror for on-chip ESD protection

This paper proposes a method aiding in low clock skew applicable to the mainstream industry clock tree synthesis (CTS) design flow. The original clock root is partitioned into several pseudo clock sources at the gate level. The automatic place and route (APR) tool may synthesize the clock tree with better performance in clock skew because each pseudo clock source drives smaller number of fan out. The proposed method is applied to a chip level clock tree network and achieves good results.

A novel ESD self-protecting symmetric nLDMOS for 60V SOI BCD process

In this work, new design techniques that aim to reduce power consumption of true single-phase clock-based (TSPC) prescalers is presented. The structure of divide-by-4/5 frequency divider is simplified, and its performance is compared with previous work to demonstrate the improvement. Simulation results show at least a 25% reduction of power consumption is achieved by the proposed unit. In the 32/33 dual modulus prescaler, a critical path cutting scheme is introduced to improve speed to the limit decided by the divide-by-4/5 unit.

An efficient clock tree synthesis method in physical design

An ultra high speed current mode logic (CML) latch is proposed in this paper. The latch uses an NMOS transistor controlled by clock signal to improve the tail current of the latching branch, so as to improve the speed of the latch. In 0.13μm CMOS technology, the divide-by-four frequency divider composed of the proposed CML latch can work under the maximum frequency of 15.2GHz, which is almost the twice of the conventional CML latch. Simultaneously, the proposed CML latch consumes only 1.3% more power than the conventional one, realizing a good compromise between speed and power.

A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic

A novel dual-directional silicon controlled rectifier (dSCR) device with dummy gate for electrostatic discharge (ESD) protection is presented. Compared with the traditional dSCR, the novel device has the desirable characteristics of dual-directional conduction, a low ESD trigger voltage, an adjustable ESD holding voltage and non-consumption of the extra area.

A novel CML latch for ultra high speed applications

MR-DCIV current has demonstrated the nondestructive capability to profile the interface states along the channel, accumulation and STI regions in high-voltage LDMOSFET. The correlation between interface state and MR-DCIV current has been studied under high voltage stresses in LDMOSFETs. Our study results show that RON degradation is mainly affected by newly-generated interface states in the STI region. Compare to the PBTI with higher gate voltage, OFF-state stress with higher drain voltage would become the worst degradation condition in an STI-based nLDMOSFETs.

Analysis of dummy-gate dual-directional SCR (dSCR) device for ESD protection

Multilevel cell storage allows two or more bits to be stored in one cell, thus reducing almost 50% of Flash memorys area without technology shrinkage. Basic concepts like sensing schemes in multilevel Flash memory are fundamental and need further research. In this paper, an innovative sensing architecture is presented, with the name of serial-parallel sensing scheme, which provides fast read speed and a medium area cost and power consumption, compared with conventional parallel and serial sensing schemes. Using 65nm technology, the new architecture performs well, almost five times as fast as serial sensing and has advantage over parallel sensing in both area and power consumption cost.

Correlation between MR-DCIV current and high-voltage-stress-induced degradation in LDMOSFETs

Low power on-chip interconnect technique is important for deep submicron SOC design. In this paper, a novel low swing drivers scheme based on charge redistribution is proposed. Significant reduction in power dissipation is achieved by dividing the full signal swing into several lower ones. The proposed circuits are especially suitable for driving multi-branch transmission wires by utilizing higher efficiency of charges. Compared with the reference design, the new scheme can reduce power dissipation by more than 66% as shown by HSPICE simulation while driving three branches. The proposed circuits have been fabricated and its effectiveness has been verified by measurement results.