Guilei Wang

Optimization of SiGe selective epitaxy for source/drain engineering in 22 nm node complementary metal-oxide semiconductor (CMOS)

SiGe has been widely used for source/drain (S/D) engineering in pMOSFETs to enhance channel mobility. In this study, selective Si1−xGex growth (0.25 ≤ x ≤ 0.35) with boron concentration of 1–3 × 1020 cm−3 in the process for 22 nm node complementary metal-oxide semiconductor (CMOS) has been investigated and optimized. The growth parameters were carefully tuned to achieve deposition of high quality and highly strained material. The thermal budget was decreased to 800 °C to suppress dopant diffusion, to minimize Si loss in S/D recesses, and to preserve the S/D recess shape. Two layers of Si1−xGex were deposited: a bottom layer with high Ge content (x = 0.35) which filled the recess and a cap layer with low Ge content (x = 0.25) which was elevated in the S/D regions. The elevated SiGe cap layer was intended to be consumed during the Ni-silicidation process in order to avoid strain reduction in the channel region arising from strain relaxation in SiGe S/D. In this study, a kinetic gas model was also applied to...

Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 22 nm node pMOSFETs

Pattern dependency of selective epitaxy of Si1 xGex (0.20 6 x 6 0.45) grown in recessed source/drain regions of 22 nm pMOSFETs has been studied. A complete substrate mapping over 200 mm wafers was performed and the transistors’ characteristics were measured. The designed SiGe profile included a layer with Ge content of 40% at the bottom of recess (40 nm) and capped with 20% Ge as a sacrificial layer (20 nm) for silicide formation. The induced strain in the channel was simulated before and after silicidation. The variation of strain was localized and its effect on the transistors’ performance was determined. The chips had a variety of SiGe profile depending on their distance (closest, intermediate and central) from the edge of the 200 mm wafer. SiGe layers with poor epi-quality were observed when the coverage of exposed Si of the chip was below 1%. This causes high Ge contents with layer thicknesses above the

Reduction of NiGe/n- and p-Ge Specific Contact Resistivity by Enhanced Dopant Segregation in the Presence of Carbon During Nickel Germanidation

This brief explores the specific contact resistivity (Pc) of NiGe/n- and p-Ge contacts with and without carbon pregermanidation implantation. It is found that in the presence of carbon, not only the thermal stability of NiGe films is improved, but also the Pc of the NiGe/n- and p-Ge contacts is reduced remarkably due to enhanced phosphorus (P) and boron (B) dopant segregation (DS) at the NiGe/Ge interface after nickel germanidation. At 500 °C germanidation temperature, the Pc values are reduced from 1.1 × 10^-4 Ω-cm² and 2.9 × 10^-5 Ω-cm² for NiGe/n- and p-Ge contacts without carbon to 7.3 × 10^-5 Ω-cm² and 1.4 × 10^-5 Ω-cm² for their counterparts with carbon, respectively.

FOI FinFET with ultra-low parasitic resistance enabled by fully metallic source and drain formation on isolated bulk-fin

The large parasitic resistance has become a critical limiting factor to on current (ION) of FinFET and nanowire devices. Fully metallic source and drain (MSD) process is one of the most promising solutions but it often suffers from intolerant junction leakage in bulk FETs. In this paper, fully MSD process on fin-on-insulator (FOI) FinFET is investigated extensively for the first time. By forming fully Ni(Pt) silicide on physically isolated fins, about 90% reduction in contacted resistivities (Rcs) and 55% reduction in sheet resistances (Rss) are achieved without obvious junction leakage degradation. As a consequence, Ion of transistor, with gate length (Lg) of 20nm, is increased 30 times, up to 547μA/μm for NMOS and 324 μA/μm for PMOS, respectively. Excellent controls of SCE and channel leakage with 47% DIBL, 32% SS and 2.5% device leakages reductions over the counterpart of conventional bulk FinFETs are also obtained. Meanwhile, the fully MSD process induces clear tensile stress into narrow fin-channel, resulting in enhanced electron mobility in NMOS. A further improvement in PMOS drive ability (486μA/μm) by using Schottky barrier source and drain (SBSD) technology is also explored.

Impacts of Back Gate Bias Stressing on Device Characteristics for Extremely Thin SoI (ETSoI) MOSFETs

In this letter, investigations of impacts of back bias stressing on extremely thin SoI MOSFETs with channel thickness varying from 11 to 4 nm are presented. For a given gate length (LG), with back bias stressing from -20 to 20 V, drain-induced barrier lowering (DIBL) with small values are obtained due to increment of carrier confinement toward the top gate for pMOSFET. While with enlargement of back bias voltage stressing from -40 to 40 V, the DIBL behaviors are different for channel thickness from 11 to 4 nm. The DIBL with channel thickness of 4 nm is consistent down to small value along with positive gate bias stressing. While for channel thickness of 7 and 11 nm, the DIBL both changes to large values at two ends of voltage stressing. In addition, subthreshold swing gets worse with more positive back gate bias (BGB) stressing. In addition, smaller channel thickness would lead to even more degraded subthreshold swing and poor gate controllability by applying a large BGB stressing. These are mainly due to high electric field in the channel induced by BGB. High positive BGB would lead to an enlargement of depletion width at the channel corner and short channel effect would get worse. In addition, high electric field is bad for channel mobility, which leads to degraded subthreshold swing.

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 1020 cm−3. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.

Mitigation of Reverse Short-Channel Effect With Multilayer TiN/Ti/TiN Metal Gates in Gate Last PMOSFETs

This letter investigates the mitigation of reverse short-channel effect (RSCE) using multilayer atomic layer deposition (ALD) TiN/PVD Ti/CVD TiN metal gates (MG) for the p-channel metal-oxide-semiconductor field-effect transistors fabricated the by gate-last process. It is found that work function (WF) of multilayer ALD titanium nitride/physical vapor deposition titanium/chemical vapor deposition titanium nitride (ALD TiN/PVD Ti/CVD TiN) MG in devices of short channels is larger than in devices of long channels. This mainly results from different ALD TiN crystal orientations for devices with different gate lengths, that is, TiN(100) for devices with short gate length, whereas TiN(111) for devices with long gate length. The WF of ALD TiN(100) is larger than TiN(111). Meanwhile, because of the property of PVD sputtering, the Ti layer is thinner in devices of short channels than in devices of long channels. Our results on MOSCAP show that the flat-band voltage (Vfb) for TiN MG with a Ti layer is reduced by 0.2 V. Taking all the aforementioned into account, Vth roll-up is suppressed as the gate length shrinks, leading to the mitigation of RSCE.

High-quality HfSiON gate dielectric and its application in a gate-last NMOSFET fabrication

HfSiON gate dielectric with equivalent oxide thickness of 10Å was prepared by reactive sputtering. It exhibits good physical and electrical characteristics, including good thermal stability up to 900°C, high dielectric constant and low gate leakage current. It was integrated with TaN metal gate in a novel gate-last process flow to fabricate NMOSFET. In the process, poly-silicon was deposited on HfSiON gate dielectric as dummy gate and replaced by TaN metal gate after source/drain formation. Because of the metal gate formation after the ion-implant doping activation at high temperature, HfSiON/TaN NMOSFET with good driving ability and excellent sub-threshold characteristics was fabricated.

Investigation on direct-gap GeSn alloys for high-performance tunneling field-effect transistor applications

GeSn alloys are investigated for high-performance tunneling device applications. Samples with relatively high Sn compositions are characterized. GeSn electronic band structures are calculated and basic material parameters are extracted. Based on the established GeSn parameter sets, direct-gap GeSn tunneling field-effect transistors are simulated and analyzed. A higher Sn composition enhances device performance, but subthreshold swing is affected by the increased leakage level. For ultra small supply voltages, device structure should be optimized to improve device characteristics.

Low frequency noise characterization of 22nm PMOS featuring with filling W gate using different precursors

Low frequency noise behavior of 22 nm Si pMOSFETs featuring with filling W gate using different precursors, i.e., SiH4 or B2H6, have been studied. It is shown that carrier number and correlated mobility fluctuations are the underlying mechanisms for the flicker noise. Moreover, devices with B2H6 W processed gate metal were found to have a higher mean trap density and scattering coefficient than SiH4 W processed gate metal. In addition, both gate-voltage-dependent and gate-voltage-independent Generation-Recombination (GR) noise peaks have been found, which are assigned to traps in the gate oxide or depletion region, respectively.