Huaxiang Yin

High performance amorphous oxide thin film transistors with self-aligned top-gate structure

We have demonstrated self-aligned top-gate amorphous oxide TFTs for large size and high resolution displays. The processes such as source/drain and channel engineering have been developed to realize the self-aligned top gate structure. Ar plasma is exposed on the source/drain region of active layer to minimize the source/drain series resistances. To prevent the conductive channel, N2O plasma is also treated on the channel region of active layer. We obtain a field effect mobility of 5.5 cm2/V·s, a threshold voltage of 1.1 V, and a sub-threshold swing of 0.35 V/decade at sub-micron a-GIZO TFTs with the length of 0.67#x00B5;m. Furthermore, a-IZO TFTs fabricated for gate and data driver circuits on glass substrate exhibit excellent electrical properties such as a field effect mobility of 115 cm2/V·s, a threshold voltage of 0.2 V, a sub-threshold swing of 0.2 V/decade, and low threshold voltage shift less than 1 V under bias temperature stress for 3 hr.

High-performance amorphous gallium indium zinc oxide thin-film transistors through N2O plasma passivation

Amorphous-gallium-indium-zinc-oxide (a-GIZO) thin filmtransistors (TFTs) are fabricated without annealing, using processes and equipment for conventional a-Si:H TFTs. It has been very difficult to obtain sound TFT characteristics, because the a-GIZO active layer becomes conductive after dry etching the Mo source/drain electrode and depositing the a-SiO2 passivation layer. To prevent such damages, N2O plasma is applied to the back surface of the a-GIZO channel layer before a-SiO2 deposition. N2O plasma-treated a-GIZO TFTs exhibit excellent electrical properties: a field effect mobility of 37cm2∕Vs, a threshold voltage of 0.1V, a subthreshold swing of 0.25V/decade, and an Ion∕off ratio of 7.

180nm gate length amorphous InGaZnO thin film transistor for high density image sensor applications

In this article, we propose a novel hybrid complementary metal oxide semiconductor (CMOS) image sensor architecture utilizing nanometer scale amorphous In-Ga-Zn-O (a-IGZO) thin film transistors (TFT) combined with a conventional Si photo diode. This approach will overcome the loss of quantum efficiency and image quality due to the downscaling of the photodiode. The 180nm gate length a-IGZO TFT exhibits remarkable short channel device performance including a low 1/ƒ noise and a high output gain, despite fabrication temperatures as low as 200°C. The excellent device performance has been achieved by a double layer gate dielectric (Al2O3/SiO2) and a trapezoidal active region formed by a tailored etching process. A self aligned top gate structure was employed for low parasitic capacitance. 3D process simulation tools were applied to optimize a four pixel CMOS image sensor structure. The results demonstrate how our stacked hybrid device approach contributes to new device strategies in image sensor architectures. We expect that this approach is applicable to numerous devices and systems in future micro- and nano-electronics.

Self-aligned top-gate amorphous gallium indium zinc oxide thin film transistors

We have demonstrated a self-aligned top-gate amorphous gallium indium zinc oxide thin film transistor (a-GIZO TFT). It had a field effect mobility of 5 cm2/V s, a threshold voltage of 0.2 V, and a subthreshold swing of 0.2 V/decade. Ar plasma was treated on the source/drain region of the a-GIZO active layer to reduce the series resistance. After Ar plasma treatment, the surface of the source/drain region was divided into In-rich and In-deficient regions. The a-GIZO TFT also had a constant sheet resistance of 1 kΩ/◻ for a film thickness of over 40 nm. The interface between the source/drain Mo metal and the Ar plasma-treated a-GIZO indicated a good Ohmic contact and a contact resistivity of 50 μΩ cm2.

Source/Drain Series-Resistance Effects in Amorphous Gallium–Indium Zinc-Oxide Thin Film Transistors

In this letter, we investigated the effects of source/drain series resistance on amorphous gallium-indium-doped zinc-oxide (a-GIZO) thin film transistors (TFTs). A linear least square fit of a plot of the reciprocal of channel resistance versus gate voltage yields a threshold voltage of 3.5 V and a field-effect mobility of about 13.5 cm2/Vldrs. Furthermore, in a-GIZO TFTs, most of the current flows in the distance range of 0-0.5 mum from the channel edge and shorter than that in a-Si:H TFTs. Moreover, unlike a-Si:H TFTs, a-GIZO TFTs did not show an intersection point, because they did not contain a highly doped ohmic (n+) layer below the source/drain electrodes.

Short Channel Characteristics of Gallium–Indium–Zinc–Oxide Thin Film Transistors for Three-Dimensional Stacking Memory

Amorphous gallium-indium-zinc-oxide (GIZO) thin film transistors with short channels of 50 nm were successfully fabricated by e-beam lithographic patterning. The GIZO thin film transistors showed a high mobility of 8.2 cm2/Vldrs with on-to-off current ratios up to 106. Excellent short channel characteristics were also obtained with a small shift of the threshold voltages and no degradation of subthreshold slopes as VDS increased, even with short channel lengths of less than 100 nm. These promising results indicate that the GIZO thin film transistors could be a candidate for selection transistors in 3-D cross point stacking memory.

Stack friendly all-oxide 3D RRAM using GaInZnO peripheral TFT realized over glass substrates

This paper reports on new concept consisting of all-oxide-based device component for future high density non-volatile data storage with stackable structure. We demonstrate a GaInZnO (GIZO) thin film transistors (TFTs) integrated with 1D (CuO/InZnO)-1R (NiO) (one diode-one resistor) structure oxide memory node element. RRAM (Resistance Random Access Memory) has provided advantages in fabrication which have made these works possible. Therefore we also suggest methods and techniques for improving the distribution in bi-stable resistance characteristics of the NiO memory node. In order to fabricate stack structures, all device fabrication steps must be possible at low temperatures. The benefits provided by low temperature processes are demonstrated by our devices fabricated over glass substrates. Our paper shows the device characteristics of each individual component as well as the characteristics of combined select transistor with 1D-1R cell. XPS analysis of NiO RRAM resistance layer deposited by ALD confirms similar conclusions to previous reports of the importance of metallic Ni content in sputtered NiO for bistable resistance switching. Also we herein propose a generalized stacked-memory structure to minimize on-chip real estate to maximize integrated density.

Electromigration effect of Ni electrodes on the resistive switching characteristics of NiO thin films

The effects of Ni and Ni0.83Pt0.17 alloy electrodes on the resistance switching of the dc-sputtered polycrystalline NiO thin films were investigated. The initial off-state resistances of the films were similar to that of Pt∕NiO∕Pt film. However, after the first cycle of switching, the off-state resistance significantly decreased in the films with Ni in the electrode. It can be attributed to the migration of Ni from electrodes to the NiO films. The improvement in data dispersion of switching parameters is explained in terms of the decrease of the effective thickness of the films resulting from the migration of Ni.

Fully transparent nonvolatile memory employing amorphous oxides as charge trap and transistor’s channel layer

A fully transparent nonvolatile memory with the conventional sandwich gate insulator structure was demonstrated. Wide band gap amorphous GaInZnO (a-GIZO) thin films were employed as both the charge trap layer and the transistor channel layer. An excellent program window of 3.5 V with a stressing time of 100 ms was achieved through the well-known Fowler–Nordheim tunneling method. Due to the similar energy levels extracted from the experimental data, the asymmetrical program/erase characteristics are believed to be the result of the strong trapping of the injected negative charges in the shallow donor levels of the GIZO film.

Nanometer-Scale Oxide Thin Film Transistor with Potential for High-Density Image Sensor Applications

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al₂O₃/SiO₂) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.