Guillaume Rosaz

High-performance silicon nanowire field-effect transistor with silicided contacts

Undoped silicon nanowire (Si NW) field-effect transistors (FETs) with a back-gate configuration have been fabricated and characterized. A thick (200 nm) Si3N4 layer was used as a gate insulator and a p++ silicon substrate as a back gate. Si NWs have been grown by the chemical vapour deposition method using the vapour–liquid–solid mechanism and gold as a catalyst. Metallic contacts have been deposited using Ni/Al (80 nm/120 nm) and characterized before and after an optimized annealing step at 400 °C, which resulted in a great decrease in the contact resistance due to the newly formed nickel silicide/Si interface at source and drain. These optimized devices show a good hole mobility of around 200 cm2 V−1 s−1, in the same range as the bulk material, with a good ON current density of about 28 kA cm−2. Finally, hysteretic behaviour of NW channel conductance is discussed to explain the importance of NW surface passivation.

Controlled growth of SiGe nanowires by addition of HCl in the gas phase

Growth of Si, Ge, and, thus, SiGe nanowires (NWs) by catalyzed chemical vapor deposition proceeds at different process conditions, preventing easy realization of axial multijunctions interesting for device realization. In this paper, we propose a common process to obtain both Si, Ge, and alloyed NWs simply by adding HCl in the gas phase. It is demonstrated that addition of HCl during the growth improves the structural quality of the SiGe NWs, avoids the tapering of NWs by decreasing the uncatalyzed growth, increases the Ge fraction of the SiGe alloy NWs, and decreases the growth rate. A qualitative model based on the experimental results is proposed to explain the role of HCl during the growth. This model can be more generally applied to explain the tendency observed in the literature concerning the growth of SiGe alloyed NWs without HCl. It is based on a competition between adsorption, decomposition, and incorporation of Si and Ge in the catalyst. This competition is mainly regulated by the gas phase com...

Vertically integrated silicon-germanium nanowire field-effect transistor

We demonstrate in this paper the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field-effect transistors (FETs). We report a threshold voltage close to 3.9 V, an ION/IOFF ratio of 104. The subthreshold slope was estimated to be around 0.9 V/decade and explained by a high traps density at the nanowire core/oxide shell interface with an estimated density of interface traps Dit ∼ 1.2 × 1013 cm−2 eV−1. Comparisons are made with both vertical Si and horizontal SiGe FETs performances.

Growth and characterization of gold catalyzed SiGe nanowires and alternative metal-catalyzed Si nanowires

The growth of semiconductor (SC) nanowires (NW) by CVD using Au-catalyzed VLS process has been widely studied over the past few years. Among others SC, it is possible to grow pure Si or SiGe NW thanks to these techniques. Nevertheless, Au could deteriorate the electric properties of SC and the use of other metal catalysts will be mandatory if NW are to be designed for innovating electronic. First, this articles focus will be on SiGe NWs growth using Au catalyst. The authors managed to grow SiGe NW between 350 and 400°C. Ge concentration (x) in Si1-xGexNW has been successfully varied by modifying the gas flow ratio: R = GeH4/(SiH4 + GeH4). Characterization (by Raman spectroscopy and XRD) revealed concentrations varying from 0.2 to 0.46 on NW grown at 375°C, with R varying from 0.05 to 0.15. Second, the results of Si NW growths by CVD using alternatives catalysts such as platinum-, palladium- and nickel-silicides are presented. This study, carried out on a LPCVD furnace, aimed at defining Si NW growth conditions when using such catalysts. Since the growth temperatures investigated are lower than the eutectic temperatures of these Si-metal alloys, VSS growth is expected and observed. Different temperatures and HCl flow rates have been tested with the aim of minimizing 2D growth which induces an important tapering of the NW. Finally, mechanical characterization of single NW has been carried out using an AFM method developed at the LTM. It consists in measuring the deflection of an AFM tip while performing approach-retract curves at various positions along the length of a cantilevered NW. This approach allows the measurement of as-grown single NWs Young modulus and spring constant, and alleviates uncertainties inherent in single point measurement.

Electrical characterisation of horizontal and vertical gate-all-around Si/SiGe nanowires field effect transistors

This paper report the technological routes used to build horizontal and vertical gate all-around (GAA) Field-Effect Transistors (FETs) using both Si and SiGe NanoWires (NWs). Horizontal Si and SiGe nanowires FETs are characterized in back gate configuration. Vertical devices using Si nanowires (NWs) show good characteristics with an I_ON/I_OFF ratio close to 10⁶ and sub-threshold slope around 145 mV/decade. Finally, vertical SiGe devices also obtained with the same technological process present an I_ON/I_OFF ratio from 10³ to 10⁴ but also poor dynamics which can be explained by the high interface traps density.