Victor Dumitriu

Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs

This paper presents a new approach to the design and analysis of NoC topologies which is based on the transaction-oriented communication methods of on-chip components. We propose two algorithms that attempt to meet the communication requirement of an on-chip application using a minimum number of network resources for the task, by generating application-specific topologies. In addition, to aid the design process of complex systems, the design method incorporates a form of predictive analysis which can estimate the degree of contention in a given system without performing detailed simulation. This predictive analysis method is used to determine the minimum frequency of operation for generated topologies, and is incorporated into the topology generation process. The proposed design method was tested using real-word applications, including an MPEG4 decoder and a multi-window display application. The generated topologies were found to offer similar or better performance when compared with regular topologies. However, the topologies generated by our method were more economical, using, on average, half the network resources of regular topologies.

Run-Time Recovery Mechanism for Transient and Permanent Hardware Faults Based on Distributed, Self-Organized Dynamic Partially Reconfigurable Systems

Field-Programmable Gate Arrays (FPGAs) are rapidly gaining popularity as implementation platforms for complex space-borne computing systems. However, such systems are exposed to cosmic radiation with levels orders of magnitude higher than terrestrial levels which can cause transient and even permanent hardware faults in on-board computing platforms. Because of this, development of effective fault mitigation methods and self-repair mechanisms has become a vital aspect for FPGA-based space-borne computing platforms. This work presents a novel method for transient and permanent fault mitigation and run-time fault recovery for commercial-grade FPGA devices with partially reconfigurable tile-based architectures. The proposed method ensures the same pre-determined recovery time for transient and permanent hardware faults through dynamic on-chip component relocation regardless of the fault type. The method makes use of fully distributed control, communication, self-synchronization and self-integration mechanisms embedded in each on-chip hardware component. Run-time collaboration between components provides relocation & fault mitigation procedures. The distributed nature of the above mechanisms excludes most central failure points which could cause non-restorable system faults. This method has been implemented, tested and verified on a Xilinx Kintex-7 FPGA platform. Results show that the proposed method is significantly more resource efficient when compared with Triple-Module Redundancy or central, software-based control mechanisms.

A modeling tool for simulating and design of on-chip network systems

The conception of Network-on-Chip (NoC) presents system designers with a new approach to the design of on-chip inter-connection structures. However, such networks present designers with a large number of design parameters and decisions, many of which are critical to the efficient operation of over-all on-chip system. To aid the design process of complex systems-on-chip, this paper presents a NoC simulation environment that has been developed and implemented using the SystemC transaction-level modeling language. The simulation environment consists of on-chip components as well as traffic generators, which can generate various types of traffic patterns. The simulation environment has also been integrated with the NoC topology generation tool being developed in our group. A set of simulation results demonstrates the types of parameters that can affect the performance of on-chip systems, including topology variations, network latency and achievable throughput. These results also verify the modeling capabilities of the proposed simulation environment.

A framework of embedded reconfigurable systems based on re-locatable virtual components

The use of modern field-programmable logic devices can help system designers achieve better cost-performance characteristics, in particular in the case of multi-task and multi-modal workloads. This is particularly true when the embedded systems are based on run-time and partially reconfigurable FPGA devices. Such devices permit a system to implement part of its functionality in virtual form, by storing circuits as configuration bit-streams. The use of such virtual components, however, imposes certain requirements on both the behaviour of the system as well as the components themselves. The work presented here analyses some of these requirements, and proposes a potential framework for designing embedded systems using virtual resources. Two examples of a system using virtual components are presented and the infrastructure overhead for supporting virtual components is analysed. It is found that such systems can be implemented efficiently, both in terms of hardware resources as well as timing performance.

SoC self-integration mechanism for dynamic reconfigurable systems based on collaborative macro-function units

For most multi-modal stream processing tasks Dynamic Reconfigurable Systems-on-Chip (SoC) have demonstrated high efficiency in cost and power. These systems utilize partial reconfiguration for dynamic adaptation to changes in the workload or in environment. Mostly, reconfiguration mechanisms are based on central resource management sub-systems deployed in a CPU-core. In this paper we propose a novel mechanism for SoC self-integration based on Collaborative Macro-Function Units (CMFU). Each CMFU consist of a function-specific IP-core combined with a Co-op unit. Co-op units allow CMFUs to co-operate with each other and provide run-time self-integration into the SoC. As well, they provide self-initiation, self-termination and self-synchronization procedures without any central control. This allows a dramatic increase in SoC flexibility, reliability and, finally, survivability. It is specifically important to mitigate hardware faults caused by radiation effects or aging of the die. The proposed mechanism was implemented and tested on a Xilinx Kintex-7 FPGA platform. It was shown that CMFUs can perform self-integration and relocation inside the FPGA almost seamlessly. The hardware overhead of the Co-op unit was relatively small (less than 10% of the entire CMFUs).

Decentralized run-time recovery mechanism for transient and permanent hardware faults for space-borne FPGA-based computing systems

One of the most important problems for mission critical space-borne computing systems employing FPGA devices is fault tolerance to transient and permanent hardware faults. In many cases, the ability for run-time self-recovery from such faults is a vital feature. This paper presents a method and mechanism for run-time recovery of FPGA-based System-on-Chip (SoC) based on Collaborative Macro-Function Units (CMFUs). Each CMFU consist of a macro-function specific data-path, control unit and circuits providing self-integration, self-synchronization and self-recovery functions for the CMFU, without centralized control. The proposed mechanism allows run-time scrubbing or relocation of faulty components of the SoC providing much higher flexibility and reliability of the system. This mechanism was implemented and tested on a Xilinx Kintex-7 FPGA platform. It was determined that the proposed approach can provide seamless run-time recovery for pipelined SoCs, while being transparent to the application.

SoPC Self-Integration Mechanism for Seamless Architecture Adaptation to Stream Workload Variations

Field-programmable gate arrays are becoming one of the implementation platforms of choice for computationally intensive embedded applications, such as multimode stream processors; such systems often exhibit poor cost-efficiency as various system modules can be idle, based on operating mode. This problem can be addressed through the use of reconfigurable computing, which allows underlying logic resources to be shared among system modules; using this approach, an application and mode specific processor can be generated at run-time. However, this generation process can interfere with application workloads; this is particularly true in the case of high data-rate stream processors. To address this problem, this brief presents a system-on-programmable-chip self-integration mechanism aimed at reconfigurable stream processors. The proposed mechanism is implemented using a distributed architecture and the multimode adaptive collaborative reconfigurable self-organized system framework. The mechanism arranges configuration, link establishment, and scheduling tasks around the stream workload, which allows for seamless run-time architecture adaptation. When compared with traditional approaches, based on central, instruction-based sequential processors, the proposed approach is shown to offer a faster (up to 10 times) link establishment and the scheduling capabilities; more importantly, the proposed mechanism can offer seamless run-time architecture adaptation by allowing the overlap of processing and configuration tasks.

Simulation environment for design and verification of Network-on-Chip and multi-core systems

The conception of Network-on-Chip (NoC) presents system designers with a new approach to the design of on-chip interconnection structures. However, such networks present designers with a large array of design parameters and decisions, many of which are critical to the efficient operation of NoC systems. To aid the design process of complex systems-on-chip, this paper presents a NoC simulation environment that has been developed and implemented using SystemC, a transaction-level modeling language. The simulation environment consists of on-chip components as well as traffic generators, which can generate various types of traffic patterns. A set of simulation results demonstrates the types of parameters that can affect performance of on-chip systems, including topology, network latency and achievable throughput. The results also verify the modeling capabilities of the proposed environment.

Mitigation of variations in environmental conditions by SoPC architecture adaptation

Run-time reconfigurable computing systems can offer increased flexibility when compared with traditional systems, a feature which can make them attractive for space-borne computing applications. This flexibility can allow a system to adapt to changes in operating conditions, such as reductions in available power, reductions in available resources (wither due to increases in task deployment, or due to permanent faults) or changes in required performance (processing rate). A unified mechanism which allows such adaptations is presented in this paper, based on the concept of architectural variants for a given algorithm; the different architectures exhibit different resource utilization, performance and power consumption attributes. This allows the system to meet various constraints through the judicious selection and deployment of an architecture variant by the appropriate reconfiguration of an implemented System-on Programmable Chip (SoPC). The adaptive capabilities of the proposed mechanism are experimentally tested on the Xilinx Kintex-7 FPGA platform (KC-705) using a video processing application aimed at 720p video streams. Three different versions of the application algorithm are implemented, allowing for performance variations between 3 and 300+ frames/second, while exhibiting a large power consumption range (from 1 mW to 81 mW).

Throughput-based network-on-chip topology generation and analysis

This paper presents a new approach to meeting communication requirements of on-chip network systems. The method is based on the transaction-oriented protocol employed by on-chip components, and the fact that latency becomes the performance-impacting factor instead of bandwidth. A network-on-chip topology generation and analysis tool is presented which has the primary aim of generating on-chip topologies that will meet a given information throughput. The proposed methodology also incorporates contention estimation into the design phase, thus reducing execution time considerably by eliminating the need for multiple generation iterations. SystemC simulation results for two multimedia applications with differing throughput requirements are presented, and the method provides comparable performance to regular topologies while using, on average, half the resources.