Engin Afacan

Adaptive sized Quasi-Monte Carlo based yield aware analog circuit optimization tool

This paper proposes an efficient Quasi-Monte Carlo based yield aware analog circuit synthesis tool with an adaptive sampling mechanism. Monte Carlo (MC) analysis is commonly preferred to estimate process variation effects on the yield of manufactured ICs. However, conventional MC requires a large number of simulations for accurate estimation. This situation causes excessive synthesis times during yield aware optimization, where many iterative variability simulations are performed. To enhance the efficiency, Infeasible Solution Elimination approach is utilized, in which yield estimation is not performed for infeasible solutions. In addition to this approach, a more efficient MC method, called Quasi-Monte Carlo (QMC), is used to generate samples from the uncertain parameter space. Thanks to the homogeneous distribution of samples, the required number of simulations is substantially reduced. Furthermore, QMC allows iterative generation of samples; hence enabling the sample size to be increased without restarting the entire simulation from the beginning. Using this property of QMC, an adaptive mechanism is proposed to determine the minimum sample size required for accurate yield estimation. The yield term is introduced as a new design constraint to the optimizer together with the electrical constraints. Finally, the developed tool offers an additional part, where a simulation budget allocation algorithm promises a more accurate yield estimation for the valuable candidates.

A two-step layout-in-the-loop design automation tool

There exists circuit sizing and layout generation tools for analog circuit designers to speed up the design process. Generally, these tools handle the circuit sizing and the layout generation processes separately, which may cause performance failures and laborious redesign iterations. Recently, new tools have been developed which simultaneously take care of circuit sizing and layout generation. However, they either suffer from long run times or limited accuracy of the utilized parasitic model. This paper presents a complete layout-aware design automation tool for analog circuits. The proposed tool combines a simulation-based circuit sizing tool with a template-based layout generation tool. The layout-induced parasitics are automatically extracted via a commercially available extractor. To reduce the run time cost originating from parasitic extraction, a two step methodology is followed, where infeasible solutions are prohibited from costly extraction process.

A deterministic aging simulator and an analog circuit sizing tool robust to aging phenomena

Analog circuit sizing has become a very challenging process due to increased non-idealities for advanced technology nodes. Moreover, reliability of circuits has become a major concern, where process variations and aging phenomena have been substantially worsened in deep-sub-micron devices. Thereby, traditional circuit optimization tools have been replaced by more complicated ones, which take reliability and variability issues into account. Efficient variability analysis and yield-aware circuit synthesis have been studied for many years, and numerous solutions have been proposed in the literature. On the other hand, aging analysis is still quite problematic in terms of accuracy and efficiency; therefore, more reliable and effective tools have emerged, especially for design automation systems. This study proposes an efficient deterministic aging simulator and an aging-aware analog circuit sizing tool.

A lifetime-aware analog circuit sizing tool

Abstract Reliability of CMOS circuits has become a major concern due to substantially worsening process variations and aging phenomena in deep sub-micron devices. As a result, conventional analog circuit sizing tools have become incapable of promising a certain yield whether it is immediately after production or after a certain period of time. Thereby, analog circuit sizing tools have been replaced by better ones, where reliability is included in the conventional optimization problem. Variation-aware analog circuit synthesis has been studied for many years, and numerous methodologies have been proposed in the literature. On the other hand, to our best knowledge, there has not been any tool that takes lifetime into account during the optimization. Besides, there are a number of different issues with lifetime-aware circuit optimization. For example, aging analysis is still quite problematic due to modeling and simulation deficiencies. Furthermore, a challenging trade-off between efficiency and accuracy is revealed during lifetime estimation in the optimization loop. Relatively expensive aging analysis is carried out for each candidate solution corresponding to a large number of simulations, so it is extremely important to deal with this trade-off. With regard to aforementioned these problems, this study proposes a novel lifetime-aware analog circuit sizing tool, which utilizes a novel deterministic aging simulator with adjustable step size. Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) mechanisms are considered during the lifetime analysis, where the NBTI model was developed via accelerated aging experiments through silicon data. As case studies, two different OTA circuits are synthesized and results are provided to discuss the proposed tool.

Sensitivity based methodologies for process variation aware analog IC optimization

With the continuous downscaling of CMOS technology over the last two decades, reliability of CMOS circuits has become a more critical design issue due to the worsening effects of process variations. Conventionally, variability analysis has been performed following the design process after which the design is modified based on the variation effects, if necessary. However, increased variation and mismatch problems have enforced designers to consider robustness as a design objective that should be maximized. Besides the variability problem, increased non-idealities with more advanced technologies have complicated circuit analysis, and caused unacceptably long design times. Therefore, design automation tools for analog circuits have become crucial to keep the synthesis time within acceptable limits even if variability analysis is included. In this paper, two different methodologies are proposed and discussed for variation aware design automation of analog circuits: Over-Design approach that is based on guard-banding the circuit performance and Variation-Aware Design approach depending on looking for more robust solutions in the dedicated search space. The superiorities of the proposed approaches are discussed via the synthesis results of a two stage OTA example.

A novel yield aware multi-objective analog circuit optimization tool

This paper proposes a novel multi-objective yield aware analog sizing tool that utilizes scrambled Quasi Monte Carlo (QMC) approach for efficient yield estimation and Strength Pareto Evolutionary Algorithm-2 (SPEA2) as a search engine. Analog circuit sizing tools have been utilized for the last two decades to overcome challenging trade-offs in analog circuit design. However, due to the variation phenomenon, some solutions at the Pareto front (PF) move towards the suboptimal region. To overcome this issue, yield aware optimization tools, where yield is given as a new design objective, have been proposed in the last decade. Conventionally, Monte Carlo (MC) approach has been used for the yield estimation. However, large sized MC analysis is a highly inefficient and time consuming process because of the numerous simulations performed during the optimization process. Rather than conventional MC, using QMC, which utilizes Low Discrepancy Sequences (LDS), enhances the synthesis time since, it promises low estimation errors with fewer number of simulations. Thanks to the QMC based variability analysis and multi-objective search engine, a yield aware PF that allows the designer to access all robust solutions can be obtained within an acceptable synthesis time.

A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool

Efficient yield estimation methods are required by yield aware automatic sizing tools, where many iterative variability analyses are performed. Quasi Monte Carlo (QMC) is a popular approach, in which samples are generated more homogeneously, hence faster convergence is obtained compared to the conventional MC. However, since QMC is deterministic and has no natural variance, there is no convenient way to obtain estimation error bounds. To determine the confidence interval of the estimated yield, scrambled QMC, in which samples are randomly permuted, is run multiple times to obtain stochastic variance by sacrificing computational cost. To palliate this challenge, this paper proposes a hybrid method, where a single QMC is performed to determine infeasible solutions in terms of yield, which is followed by a few scrambled QMC analyses providing variance and confidence interval of the estimated yield. Yield optimization is performed considering the worst case of the current estimation, thus the optimizer guarantees that the solution will satisfy the confidence interval. Furthermore, a yield ranking mechanism is also developed to enforce the optimizer to search for more robust solutions.

Reliability enhancement using in-field monitoring and recovery for RF circuits

Failure due to aging mechanisms is an important concern for RF circuits. In-field aging results in continuous degradation of circuit performances before they cause catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is not just determined by aging at the device level, but also by the slack in the specifications, process variations, and the stress conditions on each of the devices. In this paper, we present a methodology for analyzing, monitoring, and mitigating performance degradation in cross-coupled LC oscillators caused by aging mechanisms in MOSFET devices. At design time, we identify reliability hot spots and concentrate our efforts on improving these components. We aim at altering degradation patterns of important performance parameters, thereby improving the lifetime of the circuit with low area and no performance impact. We use simulations based on verified aging models to evaluate the monitoring and mitigation techniques and show that the proposed methods can increase the lifetime of the devices with no impact on the initial performance.

Model based hierarchical optimization strategies for analog design automation

The design of complex analog circuits by using flat optimization-based approaches is inefficient, even impossible, due to the high number of design variables and the growth of the cost of performance evaluation with the circuit size. Over the past two decades, top-down hierarchical design approaches have been developed and applied. They are based on hierarchical circuit decomposition and specification transmission from top-level to lower level blocks. However, such specification transmission is usually performed with little knowledge on the feasibility of the specifications, leading, therefore, to costly redesign iterations. Even if the specification transmission is successful, there is no guarantee that it is optimal in terms of e.g., power consumption or area occupation. To palliate this problem, two novel model-based hierarchical synthesis methods are proposed in this paper: ModelBased Hierarchical Optimization (MBHO) and Improved ModelBased Hierarchical Optimization (IMBHO). They are based on the concurrent design at higher and lower hierarchical levels and appropriate communication between the different processes. Experimental results on a filter example comparing the new approaches and the conventional top-down design approach are provided.

Semi-empirical aging model development via accelerated aging test

Modelling of the degradation mechanisms has a crucial role during the aging analysis, which determines the accuracy of the lifetime estimation. Conventionally, analytical and semi-empirical models are utilized during the aging analysis. Analytical models employ deterministic equations during the degradation calculation and they can be scaled for different technology nodes; hence providing flexibility. However, scaling errors and approximations during the model development may degrade the accuracy. On the other hand, semi-empirical models are generated via accelerated aging test (AAT) performed on the silicon, which often promise more reliable results for a given technology. This paper comprehensively examines the semi-empirical modelling process from test chip design to AAT experiments.