I. Faik Baskaya

A Floating-Gate-Based Field-Programmable Analog Array

A field-programmable analog array (FPAA) with 32 computational analog blocks (CABs) and occupying 3 × 3 mm2 in 0.35-μm CMOS is presented. Each CAB has a wide variety of subcircuits ranging in granularity from multipliers and programmable offset wide-linear-range Gm blocks to nMOS and pMOS transistors. The programmable interconnects and circuit elements in the CAB are implemented using floating-gate (FG) transistors, the total number of which exceeds fifty thousand. Using FG devices eliminates the need for SRAM to store configuration bits since the switch stores its own configuration. This system exhibits significant performance enhancements over its predecessor in terms of achievable dynamic range (> 9 b of FG voltage) and speed (≈ 20 gates/s) of accurate FG current programming and isolation between ON and OFF switches. An improved routing fabric has been designed that includes nearest neighbor connections to minimize the penalty on bandwidth due to routing parasitic. A maximum bandwidth of 57 MHz through the switch matrix and around 5 MHz for a first-order low-pass filter is achievable on this chip, the limitation being a “program” mode switch that will be rectified in the next chip. Programming performance improved drastically by implementing the entire algorithm on-chip with an SPI digital interface. Measured results of the individual subcircuits and two system examples including an AM receiver and a speech processor are presented.

A two-step layout-in-the-loop design automation tool

There exists circuit sizing and layout generation tools for analog circuit designers to speed up the design process. Generally, these tools handle the circuit sizing and the layout generation processes separately, which may cause performance failures and laborious redesign iterations. Recently, new tools have been developed which simultaneously take care of circuit sizing and layout generation. However, they either suffer from long run times or limited accuracy of the utilized parasitic model. This paper presents a complete layout-aware design automation tool for analog circuits. The proposed tool combines a simulation-based circuit sizing tool with a template-based layout generation tool. The layout-induced parasitics are automatically extracted via a commercially available extractor. To reduce the run time cost originating from parasitic extraction, a two step methodology is followed, where infeasible solutions are prohibited from costly extraction process.

A lifetime-aware analog circuit sizing tool

Abstract Reliability of CMOS circuits has become a major concern due to substantially worsening process variations and aging phenomena in deep sub-micron devices. As a result, conventional analog circuit sizing tools have become incapable of promising a certain yield whether it is immediately after production or after a certain period of time. Thereby, analog circuit sizing tools have been replaced by better ones, where reliability is included in the conventional optimization problem. Variation-aware analog circuit synthesis has been studied for many years, and numerous methodologies have been proposed in the literature. On the other hand, to our best knowledge, there has not been any tool that takes lifetime into account during the optimization. Besides, there are a number of different issues with lifetime-aware circuit optimization. For example, aging analysis is still quite problematic due to modeling and simulation deficiencies. Furthermore, a challenging trade-off between efficiency and accuracy is revealed during lifetime estimation in the optimization loop. Relatively expensive aging analysis is carried out for each candidate solution corresponding to a large number of simulations, so it is extremely important to deal with this trade-off. With regard to aforementioned these problems, this study proposes a novel lifetime-aware analog circuit sizing tool, which utilizes a novel deterministic aging simulator with adjustable step size. Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI) mechanisms are considered during the lifetime analysis, where the NBTI model was developed via accelerated aging experiments through silicon data. As case studies, two different OTA circuits are synthesized and results are provided to discuss the proposed tool.

A novel yield aware multi-objective analog circuit optimization tool

This paper proposes a novel multi-objective yield aware analog sizing tool that utilizes scrambled Quasi Monte Carlo (QMC) approach for efficient yield estimation and Strength Pareto Evolutionary Algorithm-2 (SPEA2) as a search engine. Analog circuit sizing tools have been utilized for the last two decades to overcome challenging trade-offs in analog circuit design. However, due to the variation phenomenon, some solutions at the Pareto front (PF) move towards the suboptimal region. To overcome this issue, yield aware optimization tools, where yield is given as a new design objective, have been proposed in the last decade. Conventionally, Monte Carlo (MC) approach has been used for the yield estimation. However, large sized MC analysis is a highly inefficient and time consuming process because of the numerous simulations performed during the optimization process. Rather than conventional MC, using QMC, which utilizes Low Discrepancy Sequences (LDS), enhances the synthesis time since, it promises low estimation errors with fewer number of simulations. Thanks to the QMC based variability analysis and multi-objective search engine, a yield aware PF that allows the designer to access all robust solutions can be obtained within an acceptable synthesis time.

A hybrid Quasi Monte Carlo method for yield aware analog circuit sizing tool

Efficient yield estimation methods are required by yield aware automatic sizing tools, where many iterative variability analyses are performed. Quasi Monte Carlo (QMC) is a popular approach, in which samples are generated more homogeneously, hence faster convergence is obtained compared to the conventional MC. However, since QMC is deterministic and has no natural variance, there is no convenient way to obtain estimation error bounds. To determine the confidence interval of the estimated yield, scrambled QMC, in which samples are randomly permuted, is run multiple times to obtain stochastic variance by sacrificing computational cost. To palliate this challenge, this paper proposes a hybrid method, where a single QMC is performed to determine infeasible solutions in terms of yield, which is followed by a few scrambled QMC analyses providing variance and confidence interval of the estimated yield. Yield optimization is performed considering the worst case of the current estimation, thus the optimizer guarantees that the solution will satisfy the confidence interval. Furthermore, a yield ranking mechanism is also developed to enforce the optimizer to search for more robust solutions.

Semi-empirical aging model development via accelerated aging test

Modelling of the degradation mechanisms has a crucial role during the aging analysis, which determines the accuracy of the lifetime estimation. Conventionally, analytical and semi-empirical models are utilized during the aging analysis. Analytical models employ deterministic equations during the degradation calculation and they can be scaled for different technology nodes; hence providing flexibility. However, scaling errors and approximations during the model development may degrade the accuracy. On the other hand, semi-empirical models are generated via accelerated aging test (AAT) performed on the silicon, which often promise more reliable results for a given technology. This paper comprehensively examines the semi-empirical modelling process from test chip design to AAT experiments.

Analog layer extensions for analog/mixed-signal assertion languages

Assertion-based methodology is gaining popularity in analog and mixed-signal (AMS) verification. Early AMS assertion languages are built on digital assertion languages. This results in limited native support to express most low-level aspects of AMS properties. We present three analog layer extensions to increase analog expressiveness in AMS assertion languages. We first describe the concept of haloes, an implicit way to handle tolerance values of analog signals in assertions. Then, booleanization of analog signals using dual-threshold is introduced to solve problems caused by fluctuations on signals. Finally, we integrate analog measurement operators into assertions. We validate our extensions using our prototype tool on a 10-bit two-stage pipelined analog-to-digital converter design.

An analog circuit synthesis tool based on efficient and reliable yield estimation

Analog circuit design has become a very challenging and time consuming process for circuit designers due to increased non-idealities and worsening variability phenomena. In order to facilitate the design process, several analog circuit sizing tools have been proposed in the literature. These tools have then led to yield-aware ones, where a certain yield is targeted. However, the type of variability analysis to be employed is still a topic of discussion due to the challenging trade-off between accuracy and efficiency of the yield analysis. Quasi-Monte Carlo (QMC) approach is one of the efficient techniques that provides efficient variability analysis via deterministic, and more importantly homogeneous sampling. The major bottleneck of the conventional QMC is that there is no practical way to calculate the estimation error. Scrambled-QMC has been utilized to obtain the error bounds of the estimation, thanks to multiple runs of randomized sample sets. However, the requirement of multiple runs substantially increases the synthesis time. To overcome this problem, this paper proposes a novel yield-aware analog circuit sizing tool, where an adaptive sample sizing algorithm for scrambled-QMC is employed in the yield estimation part.

Integrating circuit analyses for assertion-based verification of programmable AMS circuits

Digitally-programmable analog circuits provide reconfigurability and flexibility for next-generation electronic systems and modern electronic systems need such circuits more than ever. For verification of these circuits, the change in analog characteristics according to digital inputs should be monitored and checked to determine whether measured analog characteristics satisfy desired conditions in a unified analog mixed-signal (AMS) verification environment. Therefore, we integrate common analog circuit analyses into an assertion-based verification flow, and we verify time-varying analog characteristics of digitally-programmable AMS circuits. We use results of DC, AC and Fourier transform based analyses in our AMS assertion language, and monitor violations caused by any change in digital inputs. We show an application of our approach on a programmable low-pass filter circuit where cut-off frequency can be digitally controlled.

Synthesis of clock trees for Sampled-Data Analog IC blocks

This paper describes a methodology for automated design of clock trees in Sampled-Data Analog Circuits (SDACs). The current practice in the industry and academia for clock tree design of SDACs is a manual process, which is time-consuming and error-prone. Clock tree design in digital domain, however, is fully automated and is carried out by what we call Clock Tree Synthesis (CTS) software. In spite of some critical differences, SDAC clock tree design problem has fundamental similarities with its digital counterpart. As a result, we were able to construct a methodology for SDACs around a commercial digital CTS software and a set of Perl & Tcl scripts. We will explain our methodology using a 10-bit 180 MHz 2-stage ADC as a test circuit.