Gustavo Sanchez

3D-HEVC depth maps intra prediction complexity analysis

This paper presents a complexity analysis of 3D High Efficiency Video Coding (3D-HEVC) depth maps intra prediction. The 3D-HEVC inserts new coding tools in depth maps intra prediction such as Depth Intra Skip (DIS), Depth Modeling Modes (DMMs) and Segment-wise DC (SDC). Therefore, it is important to understand the complexity of each module to allow the design of new complexity reduction techniques to encode the depth maps. This paper aims to guide other works to the most time-consuming tools that could be simplified to achieve a real-time design according to the encoding context.

DFPS: a fast pattern selector for depth modeling mode 1 in three-dimensional high-efficiency video coding standard

Abstract. Depth modeling mode 1 (DMM-1) processes its prediction unit (PU) without taking into account its neighborhood. However, an extensive analysis of neighbor pattern selection showed that the processing PU could use the same pattern of its neighbors or an adaptation of these patterns. Therefore, this work proposes the DMM-1 fast pattern selector (DFPS) algorithm that includes lightweight and medium-weight DMM-1 pattern predictors. DFPS starts using the lightweight predictor, whose output is compared with a threshold and then the algorithm employs a DMM-1 refinement or the medium-weight predictor. The result of this last predictor is compared against a new threshold, where the encoder decides if the remaining patterns of the DMM-1 algorithm or only its refinement should be evaluated. Experiments evaluating DFPS encoding efficiency in the all-intra mode demonstrate that by reducing 71% and 84% of the DMM-1 patterns’ evaluation, the complexity is reduced 11.7% and 13.4%, respectively, without significantly affecting the quality of the synthesized views.

Complexity reduction by modes reduction in RD-list for intra-frame prediction in 3D-HEVC depth maps

This paper presents a complexity reduction technique for 3D High Efficiency Video Coding (3D-HEVC) using Rate-Distortion (RD) list reduction in the depth maps intra-frame prediction. In the 3D-HEVC standardization, the HEVC intra-frame prediction was inherited from texture to depth maps. However, considering depth maps simpler behavior than texture, the intra-frame prediction contains an unnecessary complexity since there is a high number of modes evaluated by their RD-cost. This paper evaluates the usage of fewer best-ranked modes in RD-list. As a case study, 23.9% of complexity reduction was achieved by reducing the Rough Mode Decision (RMD) selection and the Most Probable Modes (MPM) algorithm to the selected configuration with small impact in BD-rate.

Energy-aware light-weight DMM-1 patterns decoders with efficiently storage in 3D-HEVC

One of the major problems in Depth Modeling Mode 1 (DMM-1) hardware design is the large memory area required for storing all wedgelet patterns. This work presents four energy-aware light-weight coding techniques to reduce the memory usage and power dissipation. Experimental results show that the proposed techniques are capable of reaching a compression rate of 76.9%, representing a reduction of 140 Kbits. In the DMM-1 hardware design, this compression rate results in smaller memory, fewer memory accesses and, thus a power dissipation decrease, reaching 678 mW for ST 65nm standard cells technology.

Energy saving on DTN using trajectory inference model

Delay or Disruption Tolerant Networks (DTN) are characterized by long delays and intermittent connectivity, requiring efficient energy consumption for increasing the mobile nodes lifetime. The movements of nodes modify the network topology, changing the number of connection opportunities between nodes. This paper proposes a new technique for energy saving on DTN by using a trajectory inference model for mobile nodes powered by machine learning techniques. The objective of this work is to reduce the energy consumption of DTN using a mobility prediction method. Experimental results indicate more than 47% of energy saving on data communication applying the trajectory inference model.

A reduced computational effort mode-level scheme for 3D-HEVC depth maps intra-frame prediction

Abstract To encode the depth maps efficiently, 3D-HEVC introduced three intra-frame prediction tools: (i) Depth Intra Skip (DIS), (ii) Depth Modeling Modes (DMMs), and (iii) Segment-wise DC Coding (SDC) that raise the encoding effort. Therefore, we analyzed the most time-consuming steps at the intra-frame prediction and proposed a model-level scheme for reducing the encoding time. The most time-consuming encoding steps were the DMM-1 wedgelet search and the Rate-Distortion (RD) list evaluation in Transform-Quantization and SDC flows. Consequently, we proposed a scheme composed of two solutions for speeding up the DMM-1 and one solution for reducing the RD-list size, accelerating the RD-list evaluation. The DMM-1 speeding up solutions use the information of neighbor-encoded blocks and the data contained in the border of the encoding block to accelerate the wedgelet search. The proposed scheme reduces 31.9% the encoding time with an impact of 0.272% in the Bjontegaard Delta-rate (BD-rate), surpassing the related works.

Low-area scalable hardware architecture for DMM-1 encoder of 3D-HEVC video coding standard

This work presents a low-area scalable architecture for the Depth Modelling Mode 1 (DMM-1) encoder of the 3D High Efficiency Video Coding (3D-HEVC) standard, removing the refinement stage. This simplification causes a small BD-rate increase (0.09%) but a significant reduction in memory usage of 30%. The scalable architecture can support different block sizes. Synthesis results for ST 65 nm Standard Cells technology show that the designed structure is capable of reaching real-time processing of HD 1080 p videos for all block sizes.

Edge-aware depth motion estimation — A complexity reduction scheme for 3D-HEVC

This work presents the Edge-Aware Depth Motion Estimation (E-ADME), a complexity reduction scheme developed for depth maps coding on 3D High Efficiency Video Coding (3D-HEVC). This scheme focuses on obtaining an execution time reduction while keeping a high quality of the encoded depth map. E-ADME starts classifying each encoding depth block as edge or homogeneous. If the block is classified as an edge, then the Test Zone Search (TZS) is applied because edges require expensive comparisons to find the best block match. Otherwise, the scheme applies an Iterative-Small Diamond Search Pattern (I-SDSP), which is a lightweight center-biased algorithm for efficient encoding of homogeneous blocks. The proposed solution was capable of achieving a time saving of 6.9% in depth maps coding, increasing less than 0.15% the BD-rate of the synthesized view.

Depth modeling modes complexity control system for the 3D-HEVC video encoder

This paper presents a complexity control system for depth maps intra-frame prediction of the 3D-High Efficiency Video Coding (3D-HEVC) standard. The proposed system uses a Proportional-Integral-Derivative controller over the Simplified Edge Detector heuristic to skip the Depth Modeling Modes (DMMs) evaluation dynamically according to a defined target rate. When analyzing the proposed system under Common Test Conditions, the proposed controller stabilizes the system to the target rate (i.e., the percentage of DMMs evaluation) after encoding a few frames, with negligible encoding efficiency impacts. The BD-rate degradation varies from 0.50% to 0.20%, on average, when the target rates vary from 5% to 15%. These target rates imply in an aggressive reduction in the DMMs evaluations, skipping the DMMs from 85% to 95% of the cases.

Real-time simplified edge detector architecture for 3D-HEVC depth maps coding

This paper introduces the Simplified Edge Detector (SED) architecture for 3D-HEVC depth maps coding. The SED algorithm classifies the encoding block as homogeneous or edge. When SED classifies the encoding block as homogeneous, the encoding is simplified skipping the bipartition modes evaluation. This approach is capable of reducing 96.7% the bipartition modes evaluation with a drawback of only 0.94% in BD-rate. The SED hardware is capable of providing the decision for all available blocks inside a 32×32 block in only 34 cycles, with a power dissipation of only 25 μW per frame, when synthesized for 65 nm ST standard cells technology.