Ramon Fernandes

Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization

This paper presents Tiny NoC, which is a scalable and efficient 3D mesh architecture developed to minimize latency and NoC area. First, we show a theoretical analysis of latency and area occupancy to demonstrate Tiny NoC efficiency when compared to a basic mesh NoC. Then, we select a set of synthetic and mapping independent traffic with several injection rates to analyze the advantages and weaknesses of Tiny NoC. The experimental results highlight that Tiny NoC always reduces area occupancy and for several cases it provides latency minimization.

A security aware routing approach for NoC-based MPSoCs

Malicious applications target Multi-Processors System-on-Chip (MPSoCs) to capture sensitive information or disrupt normal operation; therefore, security is now a design requirement for MPSoC design. Network-on-Chip (NoC) is a key communication structure to aid in the overall MPSoC protection. Firewall-based NoC protection allows data exchange monitoring and controlling according to the MPSoC security policy. Secure NoCs enable to detect and prevent a broad range of software-based attacks. However, complex security policies may turn firewalls costly. This paper proposes a protection technique based on the NoC routing algorithm. By manipulating the routing of packets, security zones can be built. Our routing algorithm prioritizes communication among paths deemed secure while guaranteeing deadlock freedom. We evaluate the scalability of the proposed technique using synthetic and real application scenarios, as well as the security of the proposed technique.

3D-HEVC depth maps intra prediction complexity analysis

This paper presents a complexity analysis of 3D High Efficiency Video Coding (3D-HEVC) depth maps intra prediction. The 3D-HEVC inserts new coding tools in depth maps intra prediction such as Depth Intra Skip (DIS), Depth Modeling Modes (DMMs) and Segment-wise DC (SDC). Therefore, it is important to understand the complexity of each module to allow the design of new complexity reduction techniques to encode the depth maps. This paper aims to guide other works to the most time-consuming tools that could be simplified to achieve a real-time design according to the encoding context.

A non-intrusive and reconfigurable access control to secure NoCs

Following the current trend in the semiconductor industry (MPSoC) and the massive advances presented by all things interconnected (Internet of Things), a massive quantity of private and metadata is being transferred through insecure channels. In the industry, almost no attention is given to the amount of data that can be collected from different individuals, just by getting access to their house appliances. With that in mind, this paper proposes a non-intrusive and reconfigurable access control architecture for Networks-on-Chip (NoCs). This architecture comprises firewalls, which are capable of filtering both incoming and outgoing network traffic by analyzing packet information and verifying a traffic initiators access permission, providing a secure environment that is capable of protecting the user data. The firewalls have approximately 12% of the router area. When the number of routers increases, the firewall area overhead grows slightly, up to only 16% in NoCs with 64 routers.

Towards risk aware NoCs for data protection in MPSoCs

Multi-Processors Systems-on-Chip (MPSoCs), as a key technology enabler of the new computation paradigm Internet-of-Things (IoT), are currently exposed to attacks. Malicious applications can be downloaded at runtime to the MPSoC, infecting IP-blocks connected to a Network-on-Chip (NoC) and opening doors to perform Timing Side Channel Attacks (TSCA). By monitoring the NoC traffic, an attacker is able to infer the sensitive information, such as secret keys. Previous works have shown that NoC routing can be used to avoid attacks. In this paper we propose GRaNoC, a NoC architecture able to monitor and evaluate the risk of the communication paths inside the NoC. Sensitive traffic is exchanged to minimal low-risk paths defined at runtime. We propose five types of dead-lock free risk-aware routing algorithm and evaluate the security, performance and cost under several synthetic and SPLASH-2 benchmarks. We show that our architecture is able to guarantee secure paths during runtime while adding only low cost and performance penalties to the MPSoC.

Smart Reconfiguration Approach for Fault-Tolerant NoC Based MPSoCs

Newest technologies of integrated circuits fabrication allow billions of transistors arranged in a single chip enabling to implement a complex parallel system, which requires a high scalable and parallel communication architecture, such as a Network-on-Chip (NoC). These technologies are very close to physical limitations increasing faults in manufacture and at runtime. Thus, it is essential to provide a fault recovery mechanism for NoC operation in the presence of faults. The preprocessing of the most probable fault scenarios and flits retransmission capability enable to anticipate the calculation of deadlock-free routings, reducing the time necessary to interrupt the system in a fault occurrence and maintaining links operating with retransmission capability. This work proposes a smart decisions mechanism for errors on NoC links, which is composed of a hardware part implemented into the links and routers, and a software part implemented inside an operating system kernel of each processor. The mechanism defines thresholds where is better to reconfigure the NoC or to retransmit flits with errors. Experimental results, with several NoC sizes and some error models, suggest when is better to reconfigure the NoC and when is better to maintain some links operating with eventual faults.

Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs

Multiprocessor System-on-Chip (MPSoC) based on Network-on-Chip (NoC) integrates a large amount of Processor Elements (PEs) to fulfill the performance requirements of several applications. These applications are composed of a set of intercommunicating tasks, which are dynamically mapped onto PEs of the target architecture. However, the efficient task-mapping requires some previous steps, among them partitioning, which organizes tasks considering their interaction before applying a mapping process. This paper introduces Partition Reduce (PR) - a task partitioning approach based on the MapReduce algorithm targeting homogeneous NoC based MPSoCs. We analyze the efficiency of PR for energy consumption (EC) minimization and load balance (LB). The results obtained from a set of experiments, with large number of tasks, demonstrate that PR is more effective on processing time and result quality when compared to the classic Simulated Annealing (SA). In addition, PR produces partitions with low energy consumption and rigorous load balance.

Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applications

Parallel applications are essential for efficiently using the computational power of a Multiprocessor System-on-Chip (MPSoC). Unfortunately, these applications do not scale effortlessly with the number of cores because of synchronization operations that take away valuable computational time and restrict the parallelization gains. Moreover, synchronization is also a bottleneck due to sequential access to shared memory. We address this issue and introduce ”Subutai”, a hardware/software (HW/SW) architecture designed to distribute essential synchronization mechanisms over the Network-on-Chip (NoC). It includes Network Interfaces (NIs), drivers and a custom library of a NoC-based MPSoC architecture that speeds up the essential synchronization primitives of any legacy parallel application. Besides, we provide a fast simulation tool for parallel applications and a HW architecture of the NI. Experimental results with PARSEC benchmark show an average application speedup of 2.05 compared to the same architecture running legacy SW solutions for 36% overhead of HW architecture.

A security-aware routing implementation for dynamic data protection in zone-based MPSoC

This work proposes a secure Network-on-Chip (NoC) approach, which enforces the encapsulation of sensitive traffic inside the asymmetrical security zones while using minimal and non-minimal paths. The NoC routing guarantees that the sensitive traffic communicates only through trusted nodes, which belong to a security zone. As the shape of the zones may change during operation, the sensitive traffic must be routed through low-risk paths. The experimental results show that this proposal can be an efficient and scalable alternative for enforcing the data protection inside a Multi-Processor System-on-Chip (MPSoC).

Architectural exploration of last-level caches targeting homogeneous multicore systems

The Last-Level Cache (LLC) influences the overall system performance and power dissipation in multicore systems significantly. This paper evaluates five LLC architectures targeting execution time, dynamic and static power dissipation, and area consumption. They are measured using the widely adopted PARSEC benchmark suite for parallel shared-memory systems. Employing Gem5 full-system simulator and 32 nm technology characterization of the McPAT framework, this work had two interesting findings: (i) the shared LLC has the overall best performance under the PARSEC parallel workload, even for applications with less than 20% of shared data. (ii) A privately accessed cache can reduce up to 20 times the dynamic power dissipation on 32 nm technology and 25 times the area consumption when compared to shared-accessed caches.