Gyu Moon

An enhancement-mode MOS voltage-controlled linear resistor with large dynamic range

It is shown that the depletion-mode linear resistor of Babanezhad and Temes (IEEE J. Solid-State Circuits, vol. SC-19, p.932-8, 1984) can be implemented in enhancement-mode devices. This allows a large increase in the dynamic range of the resistors. By inserting a bias source, the linearity can also be improved. A layout and experimental results on the resulting IC are included. >

VLSI implementation of synaptic weighting and summing in pulse coded neural-type cells

Presents the hardware realization for synaptic weighting and summing using pulse-coded neural-type cells (NTCs). The basic information processing element (NTC) encodes the information into the form of pulse duty cycles using voltage-controlled resistors, for which a pulse duty cycle modulation technique is proposed. Summation is executed by a simple capacitor circuit as a current integrator. Layouts and measurements on a fabricated integrated design are included.

Linear bilateral CMOS resistor for neural-type circuits

A previous CMOS bilateral linear resistor is analyzed and shown to be reducible from four to two transistors with improved linearity. This is developed for neural-type circuits to allow its use in emulating both excitatory and inhibitory voltage variable synapses. Simulation results using parameters of MOSIS transistors are presented to verify the theory.

An efficient path-based equivalent circuit model for design, synthesis, and optimization of power distribution networks in multilayer printed circuit boards

In high-speed printed circuit boards, the decoupling capacitors are commonly used to mitigate the power-bus noise that causes many signal integrity problems. It is very important to determine their proper locations and values so that the power distribution network should have low impedance over a wide range of frequencies, which demands a precise power-bus model considering the decoupling capacitors. However, conventional power-bus models suffer from various problems, i.e., the numerical analyzes require huge computation while the lumped circuit models show poor accuracy. In this paper, a novel power-bus model has been proposed, which simplifies the n-port Z-parameters of a power-bus plane to a lumped T-network circuit model. It exploits the path-based equivalent circuit model to consider the interference of the current paths between the decoupling capacitors, while the conventional lumped models assume that all decoupling capacitors are connected in parallel, independently with each other. It also models the equivalent electrical parameters of the board parasitic precisely, while the conventional lumped models employ only the inter-plane capacitance of the power-ground planes. Although it is a lumped model for fast and easy calculation, experimental results show that the proposed model is almost as precise as the numerical analysis. Consequently, the proposed model enables a quick and accurate optimization of power distribution networks in the frequency domain by determining the locations and values of the decoupling capacitors.

Hysteresis turn-on-off voltages for a neural-type cell

Bounds on the range of input voltages which lead to hysteresis in a neural-type cell are presented. These are important to the field of neural-type networks which operate on pulses, as do biological ones, since the presence of hysteresis allows for coding of the pulses. Since design equations have not been readily available for NTCs (neural-type cells), the authors formulate equations for V/sub 1low/ and V/sub 1high/ which make certain in terms of circuit design parameters. With the voltages determined, they are in a better position to make engineering designs of pulse coded neural-type networks.<<ETX>>

Smartphone household wireless electroencephalogram hat

Rudimentary brain machine interface has existed for the gaming industry. Here, we propose a wireless, real-time, and smartphonebased electroencephalogram (EEG) system for homecare applications. The systemuses high-density dry electrodes and compressive sensing strategies to overcome conflicting requirements between spatial electrode density, temporal resolution, and spatiotemporal throughput rate. Spatial sparseness is addressed by close proximity between active electrodes and desired source locations and using an adaptive selection of N active among 10N passive electrodes to form m-organized random linear combinations of readouts, m ≪ N ≪ 10N. Temporal sparseness is addressed via parallel frame differences in hardware. During the design phase, we took tethered laboratory EEG dataset and applied fuzzy logic to compute (a) spatiotemporal average of larger magnitude EEG data centers in 0.3 second intervals and (b) inside brainwave sources by Independent Component Analysis blind deconvolution without knowing the impulse response function. Our main contributions are the fidelity of quality wireless EEG data compared to original tethered data and the speed of compressive image recovery. We have compared our recovery of ill-posed inverse data against results using Block Sparse Code. Future work includes development of strategies to filter unwanted artifact from high-density EEGs (i.e., facial muscle-related events and wireless environmental electromagnetic interferences).

A new GHz CMOS cellular oscillator network

The design of a new CMOS cellular oscillator network (CON) architecture is presented. With its simple cellular and fractal structure, this architecture can theoretically be spread in 2D or, possibly 3D with infinite number of feedback loops. Given a local disturbance from outside, these feedbacks, in turn, guarantee a uniformly distributed change in the global state as the network is based on the same cellular structure. Choosing the oscillation frequency as our state variable, and adopting a very high speed basic cell based on todays submicron CMOS technology, we present, in this paper, possibilities of using this architecture for GHz oscillators in RF communication systems. Potential benefits of this oscillator including accurate quadrature signal generation are discussed, and simulations in 0.5 /spl mu/m CMOS are presented to verify the dynamics of this architecture.

IC layout for an MOS neural type cell

CMOS implementation of a neural-type cell (NTC) is described. Two MOS transistors are used to realize the linear resistors in the NTC. The integrated NTC simulation results verify the expected behavior of the cell. Several cells with different sizes have been designed and sent for fabrication.<<ETX>>

A ultra high speed clock distribution technique using a cellular oscillator network

This paper describes a novel process-gradient insensitive GHz clock distribution technique using a Cellular Oscillator Network. With its inherent structural synchronous characteristics, the Cellular Oscillator Network can be used in microprocessors or high-speed digital logic, where ultra high speed clock distribution with picosecond order clock skew is inevitably needed. A sleeping mode technique is also presented for power minimization. This new technique is simulated and proved with typical 3 V, 0.8 /spl mu/m CMOS N-well process parameters.

CMOS design of pulse coded adaptive neural processing element using neural-type cells

The authors present the CMOS design of an adaptive neural processing element (NPE). The CMOS circuit encodes information using pulse coded neural-type cells (NTC). The synaptic junctions are realized by voltage-controlled resistors in the NTC where the conductance of these resistors determine weights. The information is coded into a form of pulse duty cycle. The pulse duty cycle modulation (PDCM) technique is briefly reviewed. Weights, expressed in terms of the pulse duty cycle, are adaptively controlled through feedback circuits using a simple differential amplifier. This differential amplifier compares the present output with a desired reference value. The difference is used to adjust the weights through changing of the equivalent resistance value of the voltage-controlled resistor in the NTC. Simulation results of simple examples verified the design concepts.<<ETX>>