Jae-Kyung Wee

Quad-Band Antenna With High Isolation MIMO and Broadband SCS for Broadcasting and Telecommunication Services

The quad-band antenna, which is composed of two compact dual-band antennas, is presented for portable media player (PMP) applications. The antenna for the broadcasting dual band (DVB-H UHF: 470-862 MHz; L: 1452-1492 MHz) is composed of a planar inverted-F antenna (PIFA) with self-complementary structure (SCS) for the broadband performance. The measured operation bandwidth of the antenna (VSWR <; 4) is 500 MHz (370-870 MHz) at UHF band and 220 MHz (1300-1520 MHz) at L band. The two-channel WLAN multiple-input-multiple-output (MIMO) antenna with high isolation performance for the telecommunication dual band (WLAN 11b: 2.4-2.5 GHz; 11a: 5.15-5.825 GHz) is composed of a PIFA operating at 2-GHz band and a loop antenna operating at 5-GHz band. The proposed antennas are fabricated in a PMP case (εr = 3.2 ).

Compact DVB-H Antenna With Broad Dual-Band Operation for PMP Applications

A dual-band (UHF: 470-862 MHz; L: 1452-1492 MHz) Digital Video Broadcasting-Handheld (DVB-H) antenna is presented. The proposed antenna is composed of a planar inverted-F antenna (PIFA) with an input impedance matching circuit. The matching circuit improves antenna performance in the broad UHF bands (470-862 MHz: 63%). The proposed antenna has omnidirectional patterns and sufficient gain (average peak gain over 470-862 MHz: 0.9 dBi) for the portable media player (PMP) applications. The antenna is contact with a PMP case (εr = 3.2), which is used as a substrate for the size reduction and compact design.

A Small-Area Low-Power Current Readout Circuit Using Two-Stage Conversion Method for 64-Channel CNT Sensor Arrays

In this paper, a small-area and low-power current readout circuit with a novel two-stage conversion method is presented for 64-channel CNT (carbon nanotube) sensor arrays. In the first stage, current of each CNT sensor is amplified by 64 active input current mirrors (AICMs). In the second stage, the amplified current is converted to a voltage level through the shared variable gain amplifier (S-VGA). Then the S-VGA output is digitalized by successive approximation register analog-to-digital converter (SAR-ADC). The proposed readout circuit significantly reduces chip area and power consumption, since VGA is shared over 64 channels and passive elements are used only in S-VGA. Fabricated chip area is 0.173 mm2 in 0.13 μm CMOS technology. Measured power consumption and linearity error are 73.06 μW and 5.3%, respectively, at the input current range of 10 nA-10 μA and conversion rate of 640 samples/s. A prototype real-time CNT sensor system was implemented using the fabricated readout circuit, and successfully detected alcohol reaction.

Low-Power 32bit×32bit multiplier design with pipelined block-wise shutdown

This paper proposes a novel low-power 32bit×32bit multiplier with pipelined block-wise shutdown scheme. When it idles, it turns off supply voltage to reduce both dynamic and static power. It shutdowns and wakes up sequentially along with pipeline stage to avoid power line noise. In idle mode, the proposed multiplier consumes 0.013mW and 0.006mW in 0.13μm and 0.09μm technologies, respectively, and it reduces power consumption to 0.07%~0.08% of active mode. As fabrication technology becomes small, power efficiency degrades in the conventional clock gating scheme, but the proposed multiplier does not. The low-power design methodology in this paper can be easily adopted in most functional blocks with pipeline architecture.

SI/PI/EMI Analysis of Through-Via Effects on Power/Ground Plane using High Dielectric Material

In this paper, we simulated and analyzed about through-vias signal integrity, (SI)/power integrity, and (PI)/electromagnetic interference (EMI) that goes through the power/ground plane which was caused by the high dielectric material that supports the embedded high value capacitors. In order to evaluate through-vias effectiveness, the simulation condition was operated on the LTCC module for mixed signal system. For the circumstance SI, delay time of signal line and signal quality significantly decrease because of higher parasitic capacitance between through-vias and anti-pads. However, in a situation where the dielectric material is chosen, the EMIs characteristic power/ground plan with embedded high dielectric material shows a better characteristic than when the low dielectric material was chosen. As a result, if the high dielectric material is applied on LTCC module, the mixed module packaging that is made with the digital IC and RF component will be realized as the optimistic design. The simulation structure takes the LTCC process designer guidebook as a basic structure and uses the HFSS/designer tool. When the dielectric constant uses 7.8 and 500, the through-vias that pass through the LTCC module are delay time of 41.4 psec and 56, respectively. When the dielectric constant of 500 is compared with 7.8, the power/ground plane impedance shows a trait lower than several GHz range and effectiveness in the rejection of the resonance mode. When uses the dielectric constant is 500, the EMI level is 7.8 and it is prove that the EMI level improves at maximum 20 dB V/m.

Effect of split power/ground planes using stitching capacitors on radiated emission

In this paper, the radiated emissions generated by various split power/ground plane structures are studied. The magnetic field and electric field over the designed test pattern are simulated. Each of the results has different field pattern by bandwidth of signal frequency, gap space or gap location of the split ground gap. To reduce the radiated emission, the method for determining the gap space and the gap location are studied based on the return current distributions. Also, the magnetic near-fields are measured by the near field EMI scan over the test board with the different value and location of the stitching capacitors. These results show that the radiated emission on split power/ground structure can be reduced by optimizing its structure. Moreover, the values and locations of the stitching capacitor should be determined to minimize the discontinuity of the return current paths.

Analysis of the EMI and SI effects on the flexible-PCBs for mobile application

The irregular shape of Flexible Printed Circuit Boards (FPCBs) causes the EMI problem or unstable signal integrity that is the important factor to system performance. The FPCBs that is used the general mobile phone is modeled and simulated in this paper And it is analyzed about the EMI and signal integrity effects as the changes of the FPCBs¿ position and shape. The structure of the FPCB consists of a base film, copper foil and coverlay. Material of the base film and a coverlay is polymide and conductor uses copper. The FPCBs are modeled as the FPCBs¿ shape inserted in folder and slide type mobile phone. In the folder type, the length of modeled FPCB is 40 mm, and the slide type FPCB is 100 mm. And according to the each case, the statuses of the FPCB when the slide is closed and open are modeled. According to the results of simulation, the strength of electric field is maximum 488.31 V/meter as the shape of FPCBs. And there are the differences in signal integrity. For the folder type, the bended FPCB model has about 2.1 dB loss at 800 MHz. And there is 0.5 dB loss as the number of bended shapes in the slide type FPCB model. The consequence is that the bended shape can cause the EMI and signal integrity problem.

Current readout circuit using two-stage amplification method for 64-channel CNT arrays

In this paper, a readout circuit with a novel two-stage amplification method is presented for current sensing of 64-channel CNT(carbon nanotube) arrays. Key blocks of the proposed readout circuit consist of a transimpedance amplifier (TIA) block and an 11-bit SAR-ADC. In whole sensing sequence, the TIA block converts sensing currents of 64-channel CNT sensors into corresponding voltage levels through 64 active input current mirrors (AICMs) and a shared variable gain amplifier (VGA). This amplification method uses only one VGA requiring a high power consumption and large area for passive elements. Therefore, the proposed two-stage amplification method can be designed with small area and low power. Also, the output of the VGA is digitalized using the SAR-ADC with adaptive resolutions based on lower bit skipping algorithm according to an input voltage level for low power operation. The readout circuit is designed with the area of 0.173 mm2 in 0.13 μm CMOS technology. The power consumption is measured about 73.06 μW at the conversion rate of 640 S/s.

One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating technique

This paper suggests a multi-level and multi-output SMPS based on a shared digital logic controller through separately operating in exclusive time period. The number of output voltages and their levels can be programmably selected for multiple power voltages. The proposed SMPS also shows a novel DPWM generator based on Pseudo Relaxation Oscillating technique. Although the shared architecture can be devised with small area and high efficiency, it has critical drawbacks that real-time control of each DPWM generators are impossible and its output voltage can be unstable. To solve these problems, a real-time current compensation scheme is proposed as a solution. A current consumption of the core block and entire block with four driver buffers was simulated about 4.9mA and 30mA at 10MHz switching frequency and 100MHz core operating frequency. Output voltage ripple is 11 mV at 3.3V output voltage. Over/undershoot voltage was HmV/19mV at 3.3V output voltage. The noise performance was simulated at 800mA @100KHz load regulation. Core circuit can be implemented small size in 700 μm × 800 μm area. For the verification of proposed circuit, the simulations were carried out with Dong-bu Hitek BCD 0.35μm technology.

PLL Jitter Analysis with Various Power Delivery Networks on a Board

Increasing frequency and reducing time margin have made desigen of power delivery neworks (PDNs) on board to be an integral part of chip designs. Power delivery network designs are usually achieved by mounting the decoupling capacitors on power plates so that the designed power impedance is relatively lower on the interested frequency ranges. But, some parts out of frequency-dependant impedance profile of power delivery networks that make the major effect on noise performances of digital, RF, and analog chips does not be very clear according to chips family. In this paper, we demonstrate the analysis of power delivery networks for the multiple voltage domains on an analog PLL jitter performance. We look for self impedances of chip mounted on board according to decoupling capacitors size, their positions, and DC-DC chip. We analyze the PLLs jitter characteristics depending on self-impedance profiles for core and IO circuit. Through this work, it is clear that the PDNs design concept which is considering inherent operation characteristics should be adapted for the efficient and costive system.