H.C. de Graaff

Measurements of bandgap narrowing in Si bipolar transistors

Abstract Theory predicts appreciable bandgap narrowing in silicon for impurity concentrations greater than about 1017 cm−3. This effect influences strongly the electrical behaviour of silicon devices, particularly the minority carrier charge storage and the minority carrier current flow in heavily doped regions. The few experimental data known are from optical absorption measurements on uniformly doped silicon samples. New experiments in order to determine the bandgap in silicon are described here. The bipolar transistor itself is used as the vehicle for measuring the bandgap in the base. Results giving the bandgap narrowing (ΔVg0) as a function of the impurity concentration (N) in the base (in the range of 4.1015–2.5 1019 cm−3) are discussed. The experimental values of ΔVg0 as a function of N can be fitted by: δV g0 = V 1 ln N N 0 + ln 2 N N 0 +C where V1, N0 and C are constants. It is also shown how the effective intrinsic carrier concentration (nie) is related with the bandgap narrowing (ΔVg0).

Unified apparent bandgap narrowing in n- and p-type silicon

Abstract In the literature, separate models exist for the apparent bandgap narrowing in n - and p -type Si, yielding a smaller bandgap narrowing in n -type than in p -type Si. Using a recently-published model, which describes both the majority and the minority carrier mobility, we have recalculated the apparent bandgap narrowing from the measurements upon which the bandgap narrowing models mentioned above are based. The results of this new interpretation show no difference in apparent bandgap narrowing in n - and p -type Si. A function describing the unified bandgap narrowing is presented.

A new analytical diode model including tunneling and avalanche breakdown

An analytical model describing reverse and forward DC characteristics is presented. It serves as a basis for a compact model for circuit simulation purposes. The model is based on the solution of the hole continuity equation in the depletion layer of a p-n junction and incorporates the following physical mechanisms: band-to-band tunneling, trap-assisted tunneling (both under forward and reverse bias), Shockley-Read-Hall recombination, and avalanche breakdown. It contains seven parameters which can be determined at one temperature. No additional parameters are needed to describe the temperature dependence. From comparisons with both numerical simulations and measurements it is found that the model gives an adequate description of the DC characteristics in both forward and reverse modes. >

Grain boundary states and the characteristics of lateral polysilicon diodes

In lateral n+p−p+ diodes made in LPCVD polycrystalline silicon films, the energy distribution of the traps at the grain boundaries is found to be U shaped. They have a density of about 1012 cm−2 and a capture cross section of about 10−16 cm2. The forward current of the diodes is ascribed to recombination, the reverse current to field-enhanced generation via these traps.

New formulation of the current and charge relations in bipolar transistor modeling for CACD purposes

New, compact analytical formulas for the current and stored charge in a vertical bipolar transistor are derived. The derivation is not based on the charge control concept, but shows how current and charge depend on minority carrier concentrations, which in turn are functions of junction voltages. In this way the influence of the built-in field, the bias-dependent transit times, and the Early effect are incorporated quite naturally. The new set of equations is the framework of a complete transistor model for computer-aided circuit design purposes.

Bandgap narrowing in silicon bipolar transistors

Martinelli [1] recently reported on measurements of theI-Vcharacteristics of silicon bipolar transistors as a function of temperature. His conclusion was that there was no evidence of bandgap narrowing in the transistors. Our experiments [2] on n-p-n transistors indicate that the bandgap does narrow for impurity concentrations aboveN = 10^{17}cm-3. The reason for this discrepancy follows from Martinellis assumption that the temperature dependence of the minority carrier mobility in the p-type base is given by T-2.6, independently of the impurity concentration, which is not justified by our measurements.

A novel frequency-independent third-order intermodulation distortion cancellation technique for BJT amplifiers

Second-harmonic control is implemented in a balanced common-emitter configuration to facilitate frequency-independent third-order intermodulation distortion cancellation. Moreover, this circuit configuration facilitates a simultaneous match for either power and linearity or noise and linearity. Experiments demonstrated an improvement of over 15 dB in the output third-order intercept point while maintaining freedom in the choice of load and source impedance.

Drift phenomena in CdSe thin film FET's

Abstract Cadmium selenide TFTs operated at fixed gate and drain bias show a slow decay of the drain current. The time dependence of this decay was found to be logarithmic. Below room temperature the rate of decrease of the number of charge carriers in the surface-channel depends only weakly on both temperature and gate bias. These results can be described with a model in which tunnelling of electrons from the channel to traps in the oxide forming the gate insulation is assumed. As time proceeds the traps are filled by this process to an ever-increasing depth. Somewhat above room temperature a strong drift of a different nature occurs. In contrast to the low temperature drift, which can be suppressed by suitable treatment, this type of drift could not be removed. It presents a serious drawback to practical applications of the CdSe TFT. In several respects the TFTs used in this investigation differ from the conventional type. Their construction is briefly discussed.

Collector models for bipolar transistors

Abstract Using Ryders formula for drift velocity vs. electric field, the d.c. field and carrier densities in the collector of a bipolar transistor are calculated analytically for all possible bias conditions. This is accomplished by modeling the majority carrier distribution. The results are compared with computer calculations and fairly close agreement is found. The analytic calculations are used to make a detailed division of the ( J c , V cb ) plane into injection, depletion and scattering-limited drift velocity (SLDV) areas. It turns out that the doping level N d and the collector width W determine the nature of this division of the ( J c , V cb ) plane.

1/f noise in polycrystalline silicon resistors

The 1/f noise in polycrystalline silicon resistors has been measured at room temperature. The resistors were manufactured in low‐pressure chemical vapor deposition films, implanted with B, P, and As and processed in two different technologies with different temperature cycles. The spectral density was essentially independent of the type of implantation and of the processing. The results can be described with Hooge’s empirical law and Kleinpenning’s model for the 1/f noise in Schottky barriers. At low doping levels Hooge’s constant turned out to be ∼4×10−3 and it decreased with increasing doping concentration, more or less as (μ/μlattice)2.