H. C. Tuan

A next generation CMOS-compatible GaN-on-Si transistors for high efficiency energy systems

CMOS-compatible 100 V / 650 V enhancement-mode high electron mobility transistors (E-HEMTs) and 650 V depletion-mode MISFET (D-MISFET) are fabricated on 6-inch GaN-on-Si wafers. These devices show excellent power converter switching performances. Both 100 V and 650 V E-HEMTs had passed industrial reliability qualifications. The importance of bulk leakage, interface quality and gate trapping in dynamic on-resistance is figured out. The device with optimized processes shows a significant reduction of the dynamic on-resistance degradation.

0.18 µm BCD technology platform with best-in-class 6 V to 70 V power MOSFETs

This paper presents a single BCD technology platform with high performance power devices at a wide range of operating voltages. The platform offers 6 V to 70 V LDMOS devices. All devices offer best-in-class specific on-resistance of 20 to 40 % lower than that of the state-of-the-art IC-based LDMOS devices and robustness better than the square SOA (safe-operating-area). Fully isolated LDMOS devices, in which independent bias is capable for circuit flexibility, demonstrate superior specific on-resistance (e.g. 11.9 mΩ-mm2 for breakdown voltage of 39 V). Moreover, the unusual sudden current enhancement appeared in the ID-VD saturation region of most of the high voltage LDMOS devices is significantly suppressed.

CMOS-compatible GaN-on-Si field-effect transistors for high voltage power applications

CMOS-compatible 100/650 V enhancement-mode FETs and 650 V depletion-mode MISFETs are fabricated on 6-inch AlGaN/GaN-on-Si wafers. They show high breakdown voltage and low specific on-resistance with good wafer uniformity. The importance of epitaxial quality is figured out in a key industrial item: high-temperature-reverse-bias-stress-induced on-state drain curent degradation. Optimization of epitaxial layers shows significant improvement of device reliability.

Investigation of parasitic BJT turn-on enhanced two-stage drain saturation current in high-voltage NLDMOS

A two-stage drain current phenomenon in saturation region, named as Id-Vd hump, has been investigated in high-voltage NMOS transistor. A parasitic BJT turn-on enhanced Id-Vd hump model is proposed and characterized by using a two-dimensional device simulation. By optimizing channel/drift-region process conditions, both parasitic BJT and impact-ionization generation can be suppressed. Both measured result and simulated result of the optimized device are presented.

AlGaN/GaN MIS-HFET with improvement in high temperature gate bias stress-induced reliability

CMOS-compatible GaN-on-silicon technology with excellent D-mode MISHFET performance is realized. A low specific contact resistance R_c (0.35 Ω-mm) is achieved by Au-free process. MIS-HFET with a gate-drain distance (L_GD) of 15 μm exhibits a large breakdown voltage (BV) (980 V with grounded substrate) and a low specific on-resistance (R _ON,_sp) (1.45 mΩ-cm²). The importance of epitaxial quality in a key industrial qualification item: high temperature gate bias (HTGB) stress-induced voltage instability issue is figured out and a breakthrough by optimizing GaN epitaxial layer for improvement of MIS-HFET is demonstrated. A low V_th shift of the optimized MIS-HFET is achieved ~ 0.14V with qualification stress condition V_G of -15 V at ambient temperature of 150 oC for 128 hours.

GaN cascode performance optimization for high efficient power applications

GaN Cascode performance optimization for high efficient power applications is presented in this paper. Analytical equations of Cascode capacitance network (Ciss, Coss, Cgd) is demonstrated and the equations accuracy is verified through experimental measurement. Analysis shows that Cascode Cgd is determined by HV D-MISFETs Cds, LV Si FETs Cgd/Coss ratio, and extra zener diode capacitance. With low intrinsic capacitance HV D-MISFETs [1-2], proper LV Si FETs selection, and extra zener diode protection, optimization for Cascode switching figure-of-merit (FOM, Ron x Qgd) is well demonstrated. 8.8X lower switching figure-of-merit than commercial best-in-class Si SJ FETs [3] is achieved, double pulse test (DPT) and hard switching PFC system verification result all indicate that GaN Cascode is the promising solution and ready for next generation energy systems.

Design of 700V LIGBT with the suppressed substrate current in a 0.5um junction isolated technology

In this paper, a 700V lateral insulated gate bipolar transistor (LIGBT) design is proposed in a junction-isolated technology. Several key properties of LIGBT, such as hole injection leakage and breakdown-voltage, are investigated by using two-dimensional numerical simulator, MEDICI. To improve vertical junction isolation capability, an extra BLN (Buried-Layer N-type) layer is inserted in-between the BLP (Buried-Layer P-type) and the P-substrate, to enhance hole potential barrier and to block substrate leakage as well as to ensure high breakdown voltage (>;700V). An optimized LIGBT with high breakdown-voltage, very low substrate-leakage (<;0.1uA/um), and low switching turn-off time, are presented and analyzed.

Improved trap-related characteristics on SiN x /AlGaN/GaN MISHEMTs with surface treatment

In this paper, the reliable SiNx/AlGaN/GaN MISHEMTs on silicon substrate with improved trap-related characteristics have been well demonstrated. The devices with our proposed treatment method showed less deep-level traps and more Si surface donors at SiNx-AlGaN interface. The trap related device characteristics are also improved by using our optimized treatment method. The devices with proposed treatment method exhibit less current collapse and better positive bias temperature stability of threshold voltage. All the results suggest that the proposed treatment method is very effective to improve the slow-trap related device reliability.

Fully-isolated NLDMOS behavior investigation during reverse recovery of parasitic diodes

The behavior of the fully-isolated laterally diffused MOSFETs (LDMOS) during reverse recovery of parasitic diodes such as buck converter or white light emitting diode (WLED) driver application was presented. The fully-isolated MOSFETs with parasitic diodes have been realized for high power application, but the related reverse recovery charge (Qrr) model fitting accuracy is still an issue for these devices. Generally, only a single model is used to cover all of the applications. However, Qrr behaviors are different between WLED driver and buck converter. In WLED output stage, two parasitic diodes within high-side switch MOS will be turned on. In buck converter application, there is only one parasitic diode within low-side switch MOS during dead time. We performed the measurement with decoupling Qrr extraction method to fit model under high-side and low-side operations. This resulted in significant Qrr model fitting accuracy improvement by 4 times.

Investigation of voltage-dependent thermal property in high-voltage drain-extended MOSFETs

In this study, a reduction in the saturation current caused by self-heating effect at high VGS is observed in a 35-V rated asymmetric DEMOSFET. The high VGS -induced the large current and raises up the device surface temperature. The Kirk-effect takes places at sufficiently high current levels (high VGS values) leading to the movement of the maximum temperature point from the gate-overlapped DE (drain-extended) region to the drain-side contact region. The drift-region resistance strongly correlates to the self-heating effect and the VK voltage is proportional to the doping concentration in the drift region. As a result, the reduced surface heating (RESURH) can be realized by the optimization of doping concentration in the drift region.