Alex Kalnitsky

A next generation CMOS-compatible GaN-on-Si transistors for high efficiency energy systems

CMOS-compatible 100 V / 650 V enhancement-mode high electron mobility transistors (E-HEMTs) and 650 V depletion-mode MISFET (D-MISFET) are fabricated on 6-inch GaN-on-Si wafers. These devices show excellent power converter switching performances. Both 100 V and 650 V E-HEMTs had passed industrial reliability qualifications. The importance of bulk leakage, interface quality and gate trapping in dynamic on-resistance is figured out. The device with optimized processes shows a significant reduction of the dynamic on-resistance degradation.

MEMS technology development and manufacturing in a CMOS foundry

MEMS technology development and MEMS manufacturing activities at TSMC are presented. Two models for process development, i.e. customer product/process “phase-in” and internally developed “platform” are discussed. The latter is a TSMC-MEMS platform for motion sensors and other devices.

Magnetic thin-film inductors for monolithic integration with CMOS

This paper presents the fabrication, design and electrical performance of magnetic thin-film inductors for monolithic integration with CMOS for DC-DC power conversion. Magnetic core inductors were fabricated using conventional CMOS processes to achieve peak inductance density of 290nH/mm2, quality factor 15 at 150MHz, current density exceeding 11 A/mm2 and coupling coefficient of 0.89 for coupled inductors.

CMOS-compatible GaN-on-Si field-effect transistors for high voltage power applications

CMOS-compatible 100/650 V enhancement-mode FETs and 650 V depletion-mode MISFETs are fabricated on 6-inch AlGaN/GaN-on-Si wafers. They show high breakdown voltage and low specific on-resistance with good wafer uniformity. The importance of epitaxial quality is figured out in a key industrial item: high-temperature-reverse-bias-stress-induced on-state drain curent degradation. Optimization of epitaxial layers shows significant improvement of device reliability.

AlGaN/GaN MIS-HFET with improvement in high temperature gate bias stress-induced reliability

CMOS-compatible GaN-on-silicon technology with excellent D-mode MISHFET performance is realized. A low specific contact resistance R_c (0.35 Ω-mm) is achieved by Au-free process. MIS-HFET with a gate-drain distance (L_GD) of 15 μm exhibits a large breakdown voltage (BV) (980 V with grounded substrate) and a low specific on-resistance (R _ON,_sp) (1.45 mΩ-cm²). The importance of epitaxial quality in a key industrial qualification item: high temperature gate bias (HTGB) stress-induced voltage instability issue is figured out and a breakthrough by optimizing GaN epitaxial layer for improvement of MIS-HFET is demonstrated. A low V_th shift of the optimized MIS-HFET is achieved ~ 0.14V with qualification stress condition V_G of -15 V at ambient temperature of 150 oC for 128 hours.

Bulk-Si with poly bump process scheme for MEMS sensors

A MEMS process scheme designed for multi- sensors is presented. This new process scheme includes a poly bump not only provides stiction prevention and gap control function, and also electrical connection between MEMS structure and routing lines. Another advantage for this scheme is a better vacuum level because all material can be high temperature annealed before final encapsulation. This study also demonstrated some MEMS devices using this new scheme, including resonators, accelerometers and magnetometers.

GaN cascode performance optimization for high efficient power applications

GaN Cascode performance optimization for high efficient power applications is presented in this paper. Analytical equations of Cascode capacitance network (Ciss, Coss, Cgd) is demonstrated and the equations accuracy is verified through experimental measurement. Analysis shows that Cascode Cgd is determined by HV D-MISFETs Cds, LV Si FETs Cgd/Coss ratio, and extra zener diode capacitance. With low intrinsic capacitance HV D-MISFETs [1-2], proper LV Si FETs selection, and extra zener diode protection, optimization for Cascode switching figure-of-merit (FOM, Ron x Qgd) is well demonstrated. 8.8X lower switching figure-of-merit than commercial best-in-class Si SJ FETs [3] is achieved, double pulse test (DPT) and hard switching PFC system verification result all indicate that GaN Cascode is the promising solution and ready for next generation energy systems.

Improved trap-related characteristics on SiN x /AlGaN/GaN MISHEMTs with surface treatment

In this paper, the reliable SiNx/AlGaN/GaN MISHEMTs on silicon substrate with improved trap-related characteristics have been well demonstrated. The devices with our proposed treatment method showed less deep-level traps and more Si surface donors at SiNx-AlGaN interface. The trap related device characteristics are also improved by using our optimized treatment method. The devices with proposed treatment method exhibit less current collapse and better positive bias temperature stability of threshold voltage. All the results suggest that the proposed treatment method is very effective to improve the slow-trap related device reliability.

Fully-isolated NLDMOS behavior investigation during reverse recovery of parasitic diodes

The behavior of the fully-isolated laterally diffused MOSFETs (LDMOS) during reverse recovery of parasitic diodes such as buck converter or white light emitting diode (WLED) driver application was presented. The fully-isolated MOSFETs with parasitic diodes have been realized for high power application, but the related reverse recovery charge (Qrr) model fitting accuracy is still an issue for these devices. Generally, only a single model is used to cover all of the applications. However, Qrr behaviors are different between WLED driver and buck converter. In WLED output stage, two parasitic diodes within high-side switch MOS will be turned on. In buck converter application, there is only one parasitic diode within low-side switch MOS during dead time. We performed the measurement with decoupling Qrr extraction method to fit model under high-side and low-side operations. This resulted in significant Qrr model fitting accuracy improvement by 4 times.

A 500nA quiescent current, trim-free, ±1.75% absolute accuracy, CMOS-only voltage reference based on anti-doped N-channel MOSFETs

In this paper, an ultra low power CMOS-only voltage reference is presented. The reference exploits the work function difference between anti-doped (flipped-gate) and standard-doped nMOS devices. These devices require no additional processing and are realizable from the basic N+ and P+ implants used to implement the standard enhancement mode MOS devices on the process. The reference is implemented as a temperature-compensated ΔVgs between anti-doped and standard-doped nMOS devices. Integrated on 0.18μm CMOS, the reference occupies less than 0.04mm2 on silicon, requires less than 500nA of quiescent current, and has a trim-free accuracy of ±1.75% which is comparable to that of the most well-behaved voltage references employing BJTs.