J. L. Yu

A next generation CMOS-compatible GaN-on-Si transistors for high efficiency energy systems

CMOS-compatible 100 V / 650 V enhancement-mode high electron mobility transistors (E-HEMTs) and 650 V depletion-mode MISFET (D-MISFET) are fabricated on 6-inch GaN-on-Si wafers. These devices show excellent power converter switching performances. Both 100 V and 650 V E-HEMTs had passed industrial reliability qualifications. The importance of bulk leakage, interface quality and gate trapping in dynamic on-resistance is figured out. The device with optimized processes shows a significant reduction of the dynamic on-resistance degradation.

Threshold voltage drift (PBTI) in GaN D-MODE MISHEMTs: Characterization of fast trapping components

VTH drift of GaN MISHEMTs under positive gate stress (PBTI) is shown to have a distinct fast component, independent of the gate dielectric material or details of the device architecture. The trap(s) responsible for this VTH degradation component are located at the GaN side of the GaN/dielectric interface. Since these fast traps have capture- and emission -times of the order of 10μs and 1ms respectively, its impact is not evident in the traditional DC characterization, yet it severely impacts device lifetime projections.

CMOS-compatible GaN-on-Si field-effect transistors for high voltage power applications

CMOS-compatible 100/650 V enhancement-mode FETs and 650 V depletion-mode MISFETs are fabricated on 6-inch AlGaN/GaN-on-Si wafers. They show high breakdown voltage and low specific on-resistance with good wafer uniformity. The importance of epitaxial quality is figured out in a key industrial item: high-temperature-reverse-bias-stress-induced on-state drain curent degradation. Optimization of epitaxial layers shows significant improvement of device reliability.

AlGaN/GaN MIS-HFET with improvement in high temperature gate bias stress-induced reliability

CMOS-compatible GaN-on-silicon technology with excellent D-mode MISHFET performance is realized. A low specific contact resistance R_c (0.35 Ω-mm) is achieved by Au-free process. MIS-HFET with a gate-drain distance (L_GD) of 15 μm exhibits a large breakdown voltage (BV) (980 V with grounded substrate) and a low specific on-resistance (R _ON,_sp) (1.45 mΩ-cm²). The importance of epitaxial quality in a key industrial qualification item: high temperature gate bias (HTGB) stress-induced voltage instability issue is figured out and a breakthrough by optimizing GaN epitaxial layer for improvement of MIS-HFET is demonstrated. A low V_th shift of the optimized MIS-HFET is achieved ~ 0.14V with qualification stress condition V_G of -15 V at ambient temperature of 150 oC for 128 hours.

GaN cascode performance optimization for high efficient power applications

GaN Cascode performance optimization for high efficient power applications is presented in this paper. Analytical equations of Cascode capacitance network (Ciss, Coss, Cgd) is demonstrated and the equations accuracy is verified through experimental measurement. Analysis shows that Cascode Cgd is determined by HV D-MISFETs Cds, LV Si FETs Cgd/Coss ratio, and extra zener diode capacitance. With low intrinsic capacitance HV D-MISFETs [1-2], proper LV Si FETs selection, and extra zener diode protection, optimization for Cascode switching figure-of-merit (FOM, Ron x Qgd) is well demonstrated. 8.8X lower switching figure-of-merit than commercial best-in-class Si SJ FETs [3] is achieved, double pulse test (DPT) and hard switching PFC system verification result all indicate that GaN Cascode is the promising solution and ready for next generation energy systems.

Improved trap-related characteristics on SiN x /AlGaN/GaN MISHEMTs with surface treatment

In this paper, the reliable SiNx/AlGaN/GaN MISHEMTs on silicon substrate with improved trap-related characteristics have been well demonstrated. The devices with our proposed treatment method showed less deep-level traps and more Si surface donors at SiNx-AlGaN interface. The trap related device characteristics are also improved by using our optimized treatment method. The devices with proposed treatment method exhibit less current collapse and better positive bias temperature stability of threshold voltage. All the results suggest that the proposed treatment method is very effective to improve the slow-trap related device reliability.