H. De Vleeschouwer

An industrial process for 650V rated GaN-on-Si power devices using in-situ SiN as a gate dielectric

This paper reports on an industrial DHEMT process for 650V rated GaN-on-Si power devices. The MISHEMT transistors use an in-situ MOCVD grown SiN as surface passivation and gate dielectric. Excellent off-state leakage, on-state conduction and low device capacitance and dynamic Ron is obtained. Initial assessment of the intrinsic reliability data on the in-situ SiN is provided.

Development of a robust 50V 0.35 /spl mu/m based Smart Power Technology using trench isolation

This paper describes a new 0.35 /spl mu/m CMOS based smart power technology. The so-called I3T50 technology belongs to a series of intelligent interface technologies developed within AMI Semiconductor over the past years. This technology is suitable for applications up to 50 V, such as automotive, peripheral and consumer applications. Trench isolation is used to isolate the devices, substantially reducing the isolation area. The set of devices available within this technology consists of n-type and p-type CMOS and DMOS devices, bipolar transistors, a high voltage floating diode, passive components, OTP memory and a set of ESD protection structures. In the future, the technology will be extended also with a modular embedded flash memory.

UltiMOS: A local charge-balanced trench-based 600V super-junction device

This paper for the first time reports on a novel “local” charge balanced trench-based super junction transistor. The local charge balance is achieved by selectively growing thin highly-doped n-type and p-type layers in a deep trench structure. The final charge-balanced trench structure is finished with an oxide-sealed airgap. Devices rated at 10A with V<inf>bd</inf>=730V and a Ron=23 mΩ.cm² are demonstrated.

Charge trapping effects and interface state generation in a 40 V lateral resurf pDMOS transistor

This paper investigates the degradation of a lateral resurf 40V pDMOS transistor under hot carrier stress using variable base charge pumping experiments. Upon stressing, the device exhibits N/sub it/ formation in the gate overlapped drift region and electron trapping in the drift region birds beak. Injection of electrons occurs at a spot approximately 50 nm from the birds beak tip. The degradation of the electrical parameters upon hot carrier stress is only correlated with the amount of injected electrons, and not with the N/sub it/ formation. The trapped electron charge will cause a walk-in of the off-state V/sub bd/.

Reliability assessment of deep trench isolation structures

An extensive investigation of the reliability of deep trench isolation structures upon reverse bias stress is performed. By using the variable base level charge pumping technique, it is shown that the degradation of the trench primarily originates from N/sub it/ formation at the inner trench corners. The reliability is improved by introducing cut corners.

Deep trench isolation for a 50 V 0.35 /spl mu/m based smart power technology

This paper describes the development of a deep trench isolation module for a new 0.35 /spl mu/m CMOS based smart power technology as well-as some major devices taking advantage of the features offered. by this deep trench isolation. The so-called I3T50 technology belongs to the third generation of intelligent interface technologies developed within AMI Semiconductor over the past years. This newest technology is suitable for applications up to 50 V, such as automotive, peripheral, industrial and consumer applications. Trench isolation is used to isolate the devices, hereby substantially reducing the isolation area. A full device library has been released within this technology (n-type and p-type CMOS and DMOS devices, bipolar transistors, high voltage floating diodes, passive components, OTP memory and a set of ESD protection structures).

A HfO 2 based 800V/300°C Au-free AlGaN/GaN-on-Si HEMT technology

Innovative 800V/300°C AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) fabricated with a 4-inch Si CMOS compatible technology are presented in this paper. High performance AlGaN/GaN MIS gated HEMT (MIS-HEMT) and passivated HEMT (i-HEMT) were fabricated using 5nm-thick HfO₂, and 30nm-thick CVD Si₃N₄ as the gate and passivation insulator, respectively. Contact resistance maps yield reduced R_c of 1.32±0.26 Ωmm for Au-free compared to 0.86±0.58 Ωmm for conventional Au-based Ohmic metallization. The off-state breakdown voltage is around 800V with a specific on-resistance of 2 mΩcm². Gate and drain leakage currents as well as dynamic I-V trapping are significantly improved with the MIS-HEMT architecture with almost no trade-off to the on-state.

Technology and design of GaN power devices

This paper reports on the technology and design aspects of an industrial DHEMT process for 650V rated GaN-on-Si power devices, using an in-situ MOCVD grown SiN as surface passivation and gate dielectric, with low interface state density and excellent TDDB. Optimization of the GaN epi stack results in very low off-state leakage (<;10nA/mm). Due to the reduction of buffer trapping, low dynamic Ron (<;10%) is obtained, both at room temperature and at high temperature.

Self-Heating Driven V th Shifts in Integrated VDMOS Transistors

Large threshold voltage shifts are observed in n-type integrated VDMOS transistors upon hot carrier stress. The effect is enhanced by the total internal temperature (ambient temperature + temperature increase due to power dissipation) of the device as well as by the gate oxide electric field. A model is presented and is used to extract the safe operating area (SOA) of the transistors. This is especially important as smart power technologies are often used in high temperature environments (up to 150-175degC), e.g. in automotive

Self-Heating Driven V>inf /inf<Shifts in Integrated VDMOS Transistors

Large threshold voltage shifts are observed in n-type integrated VDMOS transistors upon hot carrier stress. The effect is enhanced by the total internal temperature (ambient temperature + temperature increase due to power dissipation) of the device as well as by the gate oxide electric field. A model is presented and is used to extract the safe operating area (SOA) of the transistors. This is especially important as smart power technologies are often used in high temperature environments (up to 150-175degC), e.g. in automotive