H. Djahanshahi

Quantization noise improvement in a hybrid distributed-neuron ANN architecture

This work explores a useful self-scaling property of a hybrid (analog-digital) artificial neural network architecture based on distributed neurons. In conventional sigmoidal neural networks with lumped neurons, the effect of weight quantization errors becomes more noticeable at the output as the network becomes larger. However, it is shown here based on a stochastic model that the inherent self-scaling property of a distributed-neuron architecture controls the output quantization noise (error) to signal ratio as the number of inputs to an Adaline increases. This property contributes to a robust hybrid VLSI architecture consisting of digital synaptic weights and analog distributed neurons.

A unified synapse-neuron building block for hybrid VLSI neural networks

This paper presents a hybrid VLSI technique for implementation of multi-layer neural networks using a unified synapse-neuron building block. A new building block is proposed by integrating a partial S-shape neural nonlinearity within a Multiplying DAC. Circuit techniques are used to generate S-shape neural function from the combination of quadratic characteristics of four MOS devices. The proposed architecture offers design modularity and scalability, silicon area efficiency, reduced interconnection problem and increased robustness.

A robust hybrid neural architecture for an industrial sensor application

A programmable hybrid neural network architecture has been used to implement a smart optical sensor with focal-plane pattern classification for a flexible manufacturing cell environment. The network contains an integrated photosensitive array based on modified photo BJTs as input to a fully-connected multilayer feedforward (MLFF) neural classifier. The architecture features a distributed neuron realization that employs a number of active nonlinear resistor circuits operating in parallel. It minimizes the effect of parameter variations due to non-uniform device fabrication over the die surface. Moreover, due to the modularity of the architecture and locality of interconnections, synaptic density has been doubled in comparison with a conventional realization. A photosensor-classifier chip consisting of a 2-D array of 64 neural-based smart pixels and additional neural network circuits has been fabricated. The proposed architecture has been implemented in both CMOS and BiCMOS process technologies as part of a sensor optimization study.

A modular architecture for hybrid VLSI neural networks and its application in a smart photosensor

We describe a modular architecture for the VLSI implementation of multilayer neural networks using a universal hybrid building block. Based on this approach, a programmable smart photosensor is designed which is in fact a VLSI realization of a multilayer feedforward neural network with an integrated photoreceptor array using 1.2 /spl mu/m CMOS technology. Each universal building block in this architecture comprises a multiplying DAC synapse, a portion of a nonlinear distributed neuron and compact digital registers for programming and storing a synaptic weight. The proposed modular neural network architecture features design simplicity and scalability, area efficiency, reduced interconnection problems and increased robustness. Based on this architecture and using cell-level optimization, the synaptic density in this version of the neural-based smart sensor has been increased by a factor of two. This has lead to an increase in the area available for a larger and higher resolution optical input array.

Design and VLSI implementation of a unified synapse-neuron architecture

We describe the design and VLSI implementation of a unified synapse-neuron architecture for multi-layer neural networks. A new hybrid building block proposed for this purpose is formed by integrating a partial S-shape neural nonlinearity within a Multiplying DAC synapse. MDAC synapse contains modifications to simplify sign-bit circuit. Small analog circuits generate a distributed S-shape neural function by combining quadratic characteristics of four MOS transistors. The proposed modular neural network architecture features design simplicity and scalability, area efficiency, reduced interconnection problem, improved robustness and digital programmability. Based on the proposed scheme, we have considerably increased the synaptic density in the improved version of a programmable optically-coupled neural network.

A LOW-VARIATION NONLINEAR NEURON CIRCUIT

A resistive-type neuron circuit is presented that combines nonlinear characteristics of four MOS transistors to realize a saturating function. Despite circuit simplicity, characteristic variations are found to be small based on circuit analyses and fabrication measurements. Maximum variation between neurons within one chip is 1.3%, while worst-case chip-to-chip variation from 10 fabrications is 2.2%.

Quantization noise improvement in a distributed-neuron architecture

In conventional sigmoidal neural networks with lumped neurons, the effect of weight quantization becomes more apparent at the output as the network becomes larger. It is shown here, however, using a statistical approach, that the self-scaling property of a special hardware architecture with distributed neurons reduces the effect of quantization noise as the number of neuron inputs increases.

A self-scaling neural hardware structure that reduces the effect of some implementation errors

This paper explores a neural network hardware structure with distributed neurons that exhibits useful properties of self-scaling and averaging. In conventional sigmoidal neural networks with lumped neurons, the effects of weight errors and mismatches become more noticeable at the output as the network becomes larger. It is shown here that based on a stochastic model the inherent scaling property of a distributed neuron structure controls the output noise (error) to signal ratio as the number of inputs to an Adaline increases. Moreover, the averaging effect of distributed elements minimizes characteristic variations among neurons. These properties altogether provides a robust hybrid hardware with digital synaptic weights and analog neurons. A VLSI realization and an application of this neural structure are explained.

Neural-based smart CMOS sensors for on-line pattern classification applications

We review previous work on CMOS photoreceptors and neural-based smart sensors that are VLSI realization of a neural network classifier with an integrated photoreceptor array. These sensors are designed for on-line pattern classification applications requiring image capture or non-contact measurement. Photoreceptors are based on Field-Effect-Modified parasitic phototransistors in CMOS technology. Several designs have been implemented. A pre-programmed smart photosensor fabricated in 3 /spl mu/ CMOS has been successfully tested and a programmable version has been fabricated in 1.2 /spl mu/. The latest design of smart sensor is based on a novel unified synapse-neuron building block that results in a highly modular, scalable and area-efficient VLSI architecture. A test circuit containing an 8/spl times/8 photosensitive array and a fully-connected programmable neural network with N=54 inputs, m=8 hidden neurons and k=4 output neurons has been designed in the 1.2 /spl mu/ technology. Based on the new architecture synaptic density has been doubled, and we have been able to increase the size of the optical input array as well as neural classifier itself.

NEURAL NETWORK INTEGRATED CIRCUITS WITH SINGLE-BLOCK MIXED SIGNAL ARRAYS

This paper discusses the design and implementation of a family of mixed-signal neural network integrated circuits for general and application-specific purposes. Regular arrays of a nonlinearly-loaded multiplier block form the core of multilayer neural networks. Input-output circuitry and network size, however, vary depending on design applications. Some features of the present architecture are highlighted through experimental study, namely, low characteristic variations and self-scaling property of neurons and reduced interconnection problems and areas on silicon. Other design issues such as supply voltage reduction and pin limitations are discussed together with fabrication test results.