W.C. Miller

A closed-form model for the pull-in voltage of electrostatically actuated cantilever beams

A simple computationally efficient closed-form model has been developed to determine the pull-in voltage of a cantilever beam actuated by electrostatic force. The approach is based on a linearized uniform approximate model of the nonlinear electrostatic pressure and the load deflection model of a cantilever beam under uniform pressure. The linearized electrostatic pressure includes the electrostatic pressure due to the fringing field capacitances and has been derived from Meijs and Fokkemas highly accurate empirical expression for the capacitance of a VLSI on-chip interconnect. The model has been verified by comparing the results with published experimentally verified 3D finite element analysis results and also with results from similar closed-form models. The new model can evaluate the pull-in voltage for a cantilever beam with a maximum deviation of ±2% from the finite element analysis results for wide beams, and a maximum deviation of ±1% for narrow beams (extreme fringing field).

An algorithm for multiplication modulo (2/spl and/N-1)

This paper proposes an efficient algorithm for multiplication modulo (2/sup N/-1). To achieve high speed, the Wallace tree is adopted for the multiplier. The Wallace tree multiplier exhibits a more regular structure than binary Wallace tree multipliers, and comparisons with published designs demonstrates advantages of our multiplier architecture in both speed and hardware.

Pull-in voltage calculations for MEMS sensors with cantilevered beams

MEMS sensors, such as acoustic, noise and vibration transducers often employ a diaphragm or cantilevered structure as part of a variable capacitance sensor geometry. A bias voltage is necessary to ensure a linear force-capacitance range of operation. The calculation of the pull-in voltage whereby the sensing structure collapses due to electrostatic forces is an important design requirement. A linearized, uniform approximate model of the nonlinear electrostatic pressure has been developed and used in conjunction with the load deflection model of a MEMS cantilever beam under uniform pressure to develop a highly accurate model to calculate the pull-in voltage. The new model improves sensor design methodology by evaluating the pull-in voltage for a cantilever beam with a maximum deviation of less than 1% from the finite element analysis results for wide beams and for narrow beams with extreme fringing fields.

A reconfigurable digital multiplier architecture

There has been recent awareness of the drastic effects of interconnect delay in VLSI implementations, and several investigations focused on this problem have been linked directly to multiplier structures. The tree, or column compression techniques, used for partial product reduction have the severe impediment of highly irregular interconnections. A digital multiplier architecture is presented in this paper that alleviates some of the problems associated with interconnect scaling, in addition to allowing for simple variable precision reconfiguration. Regulated by a 2-bit control signal, the multiplier provides optimal circuitry for both single and double precision arithmetic, as well as fault tolerant and dual throughput single precision operation. Moreover, dynamic power management techniques allow for 75% power reduction in single precision mode, and 50% power reduction for SIMD applications.

Overlap resolution: arithmetic with continuous valued digits in hybrid architectures

Overlap resolution signal processing opens up a powerful approach to parallel analog computations with digital accuracy. This new redundant representation of signals, with continuous valued digits, carries the accuracy of analog signal processing beyond the accuracy of the analog circuitry itself. The proposed processing methodology can also be applied to an all digital system. Due to the residue nature of the analog digits, addition is residue-like and resembles carry save structures, yet it is implemented with analog circuitry. Familiar array multiplying structures are applied for multiplication when the multiplicand is overlap resolution and the multiplier is a positional number.

A 2-digit DBNS filter architecture

We have previously reported on a novel number representation using 2 bases which we refer to as the double-base number system (DBNS). Our preferred implementation uses the relatively prime bases {2,3}. If we allow the exponents of the bases to be arbitrarily large signed integers, then we can represent any real number to any arbitrary precision by a single digit DBNS representation. By representing the digit position by the exponent values, we generate a logarithmic-like representation which we can manipulate using an index calculus. A multiplier accumulator architecture for a FIR filter application has been reported which uses a half-index domain to remove the problem of addition within the index calculus. In this paper we show that using a 2-digit DBNS representation for both the input data and the filter coefficients can result in substantial hardware savings compared to both the single-digit a DBNS approach and an equivalent binary implementation of a general multiplier accumulator. In the paper we discuss the filter architecture, techniques for converting between binary and the 2-digit DBNS representations, and also the design technique used to generate the 2-digit DBNS FIR filter coefficients.

A 2-digit multidimensional logarithmic number system filterbank for a digital hearing aid architecture

This paper addresses the design and implementation of a filterbank for digital hearing aids using a multi-dimensional logarithmic number system (MDLNS). The logarithmic properties of the MDLNS allow for reduced complexity multiplication, and large dynamic range, and a multiple-digit MDLNS provides a considerable reduction in hardware complexity compared to a conventional logarithmic number system (LNS) approach. In this paper we discuss the design and implementation of both a 1-digit and 2-digit 2-D MDLNS filterbank and provide initial simulation results.

A unified synapse-neuron building block for hybrid VLSI neural networks

This paper presents a hybrid VLSI technique for implementation of multi-layer neural networks using a unified synapse-neuron building block. A new building block is proposed by integrating a partial S-shape neural nonlinearity within a Multiplying DAC. Circuit techniques are used to generate S-shape neural function from the combination of quadratic characteristics of four MOS devices. The proposed architecture offers design modularity and scalability, silicon area efficiency, reduced interconnection problem and increased robustness.

Circuit tolerances and word lengths in overlap resolution

Overlap Resolution signal processing utilizes residue-like arithmetic and opens up a powerful approach to parallel analog computations with digital accuracy. This new redundant representation of signals, with Continuous Valued Digits, carries the accuracy of analog signal processing beyond the accuracy of the analog circuitry itself. The proposed processing methodology can also be applied to a digital system. Presented tolerances for analog digit circuits and the required digit word lengths for digital circuits show the practical feasibility of Overlap Resolution.

Overlap resolution: continuous valued digits for hybrid architectures

A new redundant representation of signals with continuous valued digits enables introduction of more complex analog processing elements in a digital architecture. Continuous valued digits allow better utilization of the potential accuracy in VLSI technologies. The proposed processing methodology can be applied in an analog or in a digital system, and with either truly continuous digits, or with discrete valued digits. Coding and de-coding is relatively simple and robust. Overlap resolution signal processing utilizes residue-like arithmetic and opens up a powerful approach to parallel analog computations with digital accuracy.