H. F. Ragai

Digital on-chip phase noise measurement

In this paper, we propose an All-Digital On-Chip Phase Noise Measurement Technique. This Technique can be integrated as part of a built-in self-test (BIST) scheme for phase-locked loop (PLL)-based clock synthesizers. The proposed technique based on an all digital ΣΔ-frequency discriminator (ΣΔFD). Unlike all previously reported techniques, our proposed technique is implemented using digital-only circuits. This makes it easily integrated and scaled down for high-density microprocessor applications with modern sub 100nm technology nodes

Analysis and Modeling of RF-MEMS Disk Resonator

This paper presents the analysis and modeling of MEMS disk resonator. The main parameters that describe the operation of the disk are the quality factor, natural frequency and equivalent mass. In this work the frequency relation versus Poissons ratio of the material and a general equation for the equivalent mass of disk resonator are obtained for different vibration modes of the disk resonator. The resulting model is formulated such that it can be coded by any suitable language such as systemC, verilog-AMS or VHDL-AMS. The model is verified by ANSYS

Behavioral Modeling of RF-MEMS Disk Resonator

This paper presents behavioral modeling of RF-MEMS disk resonator through driving its equivalent circuit model. The model is operating in the first two radial contour modes and the results were verified with ANSYS. A Pierce oscillator utilizing the resonator model is designed to demonstrate the performance of the model on the oscillator. The oscillator performance like frequency and phase noise is presented

Determining the Required Pulses for Controlling the Operation of Electrostatic MEMS Converters

The main objective of this paper is to determine the required controlling pulses which control the charging and the discharging operations of the electrostatic MEMS converter. These converters found in the energy scavenging system for wireless sensor nodes. To achieve this objective, a SPICE model for the converter is implemented in order to describe its behavior. Thus the required controlling pulses are determined by simulating the interaction between the converter model and the energy scavenging system

On the utilization of strength-reduced architectures for adaptive equalizers

Traditionally adaptive equalizers for complex signals were built using a cross-coupled architecture. Strength-reduction is a technique than can be employed to trade-off power expensive multipliers, with adders. However, predicted power savings given so far are based on simplified estimates that can hardly fit a general case. This paper attempts to achieve more realistic power estimates based on actual implementation considerations and actual operating conditions. A 256-QAM decision-feedback equalizer (DFE) with 5 complex taps was taken as a case study. Simulation results indicate that the achieved savings could be channel dependent depending on the utilized multipliers.

Modeling of Q – V Diagram Using SPICE for Electrostatic MEMS Converter Found in Energy Scavenging Systems

The objective of this paper is to model the behavior of an electrostatic MEMS converter using its Q – V diagram. This model is used to sense the required instants to charge and discharge the converter. By this way the design of the converter’s controller circuit can be carried out. The converter model is implemented using SPICE circuit simulator based on discrete components. As a result, the charging and discharging instants of the converter are determined.

Fabrication and Test of Electrostatic MEMS Converter Found in Energy Scavenging Systems

This paper introduces the steps for fabricating an electrostatic MEMS converter found in energy scavenging systems. The fabrication carried out at Rensselaer Polytechnic Institute (RPI) clean room, Troy, New York, USA. The testing results for the fabricated converter are presented. The main objective of fabricating and testing the electrostatic MEMS converter is to verify the new idea of enhancing its output power by including the effect of its parallel capacitance in the output power equation.

Digital enhancement of frequency synthesizers

In this paper, we propose an All-Digital On-Chip Phase Noise Measurement Technique. This Technique can be integrated as part of a built-in self-test (BIST) scheme for phase-locked loop (PLL)-based clock synthesizers. The proposed technique based on an all digital ΣΔ-frequency discriminator. Unlike all previously reported techniques, our proposed technique is implemented using digital-only circuits and can report digital numbers corresponding to the close in phase noise level of the PLL to a digital BIST controller. This makes it easily integrated and scaled down for high-density microprocessor applications with modern sub 100nm technology nodes.

Performance Enhancement of Gap Closing Electrostatic MEMS Converters

This paper proposes new ideas to enhance the output power of the gap closing electrostatic MEMS converters. This is done by including the effect of the parallel capacitance of the converter in the output power equation. In addition the output power of the converter has increased by increasing the converter thickness