Emad Hegazi

A Low-Power Wideband CMOS LNA for WiMAX

In this brief, the design of a low-power inductorless wideband low-noise amplifier (LNA) for worldwide interoperability for microwave access covering the frequency range from 0.1 to 3.8 GHz using 0.13-mum CMOS is described. The core consumes 1.9 mW from a 1.2-V supply. The chip performance achieves S11 below -10 dB across the entire band and a minimum noise figure of 2.55 dB. The simulated third-order input intercept point is -2.7 dBm. The voltage gain reaches a peak of 11.2 dB in-band with an upper 3-dB frequency of 3.8 GHz, which can be extended to reach 6.2 GHz using shunt inductive peaking. A figure of merit is devised to compare the proposed designs to recently published wideband CMOS LNAs

A Third-Order 9-Bit 10-MHz CMOS

We present a wideband architecture for DeltaSigma modulators using a single active stage and two switched capacitor passive stages. The mixed active-passive implementation has performance advantages over traditional switched-capacitor (SC) or continuous-time implementations, particularly for high-resolution, wideband applications with high sampling rates and moderate oversampling ratios. Design insensitivity to clock jitter and process variations is achieved by the good choice of the modulator architecture. The proposed modulator is designed in 0.13-mum CMOS technology and meets all major requirements for application in IEEE 802.16 wireless MAN receivers. Circuit simulations show that the modulator with a single bit quantizer consumes 5.5 mW from a 1.2-V power supply and achieves a 9-bit resolution over a 10-MHz bandwidth at an OSR of 32. Good performance is also achieved for lower bandwidth applications.

\Delta \Sigma

This brief presents a multimodulus frequency divider with division ratio between 64 and 127 fabricated in 90-nm CMOS. By using a load-switching technique, high operating frequency, and low power static divider was achieved. The divider consists of six 2/3 divider stages. The maximum operating frequency is 4.7 GHz with current consumption 2.3 mA at low voltage supply 1.2 V and rms cycle-to-cycle jitter lower than 1 ps

Modulator With One Active Stage

In this paper, we propose an All-Digital On-Chip Phase Noise Measurement Technique. This Technique can be integrated as part of a built-in self-test (BIST) scheme for phase-locked loop (PLL)-based clock synthesizers. The proposed technique based on an all digital ΣΔ-frequency discriminator (ΣΔFD). Unlike all previously reported techniques, our proposed technique is implemented using digital-only circuits. This makes it easily integrated and scaled down for high-density microprocessor applications with modern sub 100nm technology nodes

A Multigigahertz Multimodulus Frequency Divider in 90-nm CMOS

This paper presents a CMOS low-voltage bandgap reference circuit with improved power supply rejection (PSR). The analysis of the reference circuit shows the required condition to achieve high PSR. The proposed circuit incorporates a feedback loop to insure that the condition for high PSR is achieved across process variations and temperature drifts. The design has been implemented in 130nm CMOS process. It consumes 70µA from a single 1.2V supply. Simulation results show an improvement of more than 15dB in low frequency PSR due to the additional feedback loop. The theoretical and simulation results are in close agreement.

Digital on-chip phase noise measurement

In this paper, we study transimpedance amplifiers for capacitive sensing applications with a focus on Intravascular Ultra Sound (IVUS). We employ RF noise cancellation technique on capacitive feedback based transimpedance amplifiers. This technique eliminates the input-referred noise of TIAs completely and enhances the dynamic range of front-end electronics. Simulation results verify the proposed technique used in two different TIA topologies employing shunt-shunt feedback.

A low-voltage CMOS bandgap reference circuit with improved power supply rejection

In this paper, we propose all-digital frequency synthesizer architecture, based on an all-digital SigmaDelta-frequency discriminator. The new all-digital synthesizer is compared to previously published work. The architecture of the SigmaDelta-frequency discriminator is verified using behavioral simulation

Design of low noise transimpedance amplifier for Intravascular Ultrasound

This paper reports on the design of a low phase noise 76.8MHz AlN-on-silicon reference oscillator using SiO 2 as temperature compensation material. The paper presents profound theoretical optimization of all the important parameters for AlN-on-silicon width extensional mode resonators, filling into the knowledge gap targeting the tens of megahertz frequency range for this type of resonators. Low loading CMOS cross coupled series resonance oscillator is used to reach the-state-of-the-art LTE phase noise specifications. Phase noise of -123dBc/Hz at 1kHz, and -162dBc/Hz at 1MHz offset is achieved. The oscillator?s integrated root mean square RMS jitter is 106fs (10kHz to 20MHz), consuming 850µA, with startup time of 250µs, and a figure-of-merit FOM of 216dB. This work offers a platform for high performance MEMS reference oscillators; where, it shows the applicability of replacing bulky quartz with MEMS resonators in cellular platforms.

An all-digital /spl Sigma//spl Delta/-frequency discriminator of arbitrary order

In this brief, we propose a technique for Delta-Sigma (ΔΣ) noise cancelation in fractional-N phase-locked loops (PLLs). The proposed method performs noise cancelation for both the shaped noise generated by the ΔΣ modulator and the downfolded noise due to charge pump (CP) nonlinearity. By precoding the CP control pulses, the added hardware complexity is minimal compared with conventional cancelation, whereas noise reduction is large. The proposed method is verified through the system design of a 2.5-GHz ΔΣ fractional-N PLL. Time-domain simulations show 20-dB noise reduction for the downfolded noise when applying the proposed cancelation.

A 76.8 MHz temperature compensated MEMS reference oscillator for wireless handsets

Based on the understanding of the relation between the shape of the LC VCO tuning curve and the varactor characteristics, a technique using an array of unequal varactors with different bias was found to obtain a truly linear tuning curve. An LC VCO was designed using TSMC 0.13 mum 1.2V/3.3V IO process, the VCO frequency varies from 2 - 2.34 GHz as its control voltage varies from 0 - 1.2V. The tuning gain was KVCO = 275MHz/Vplusmn6.5%.