H. Khan

Quantum Transport Simulation of Experimentally Fabricated Nano-FinFET

We have utilized the contact-block-reduction (CBR) method, which we extended to allow a charge self-consistent scheme, to simulate experimentally fabricated 10-nm-FinFET device. The self-consistent CBR simulator has been modified to simulate devices with channels along arbitrary crystallographic orientation. A series of fully quantum-mechanical transport simulations has been performed. First, the fin extension length and doping profile have been calibrated to match the experimental data. The process control window for the threshold voltage as a function of fin extension has been extracted for the considered device. Then, a set of transfer characteristics and gate leakage currents have been calculated for different drain voltages. The simulation results have been found to be in good agreement with the experimental data in the subthreshold regime. The device turn-off and turn-on behavior has been examined for different fin widths: 12 (experimental), 10, 8, and 6 nm. Finally, the subthreshold slope degradation at high temperatures has been studied

Approaching Optimal Characteristics of 10-nm High-Performance Devices: A Quantum Transport Simulation Study of Si FinFET

We utilized a fully self-consistent quantum mechanical simulator based on the contact block reduction (CBR) method to optimize a 10 nm FinFET device and meet the International Technology Roadmap for Semiconductors (ITRS) projections for double-gate high-performance logic technology devices. We found that the device ON-current approaching the value projected by the ITRS can be obtained using a conventional unstrained Si channel and a SiO2 gate insulator. We also performed a detailed analysis of the gate leakage under different bias conditions. Our simulation results show that the quantum mechanical effects significantly enhance the intrinsic switching speed of the device. In our simulations, quantum confinement in both the gates and the channel has been taken into account self-consistently. The obtained theoretical value of the intrinsic switching speed for the considered FinFET device exceeds the ITRS-projected value.

Simulation of the Impact of Process Variation on the Optimized 10-nm FinFET

We examined the influence of process variation on device performance of the optimized 10-nm FinFET device using a fully self-consistent quantum-mechanical transport simulator based on the contact block reduction method. Sensitivity of the on-current, leakage currents, threshold voltage, drain-induced barrier lowering, and subthreshold swing for the optimized FinFET to process variation at room temperature have been investigated. Subthreshold source-to-drain leakage current is found to be the most sensitive parameter to process variation. Gate leakage current has been analyzed for both poly-Si gates and gates with the work function of 4.35 eV. For poly-Si gates, the gate leakage is found to influence the subthreshold swing below or at a gate oxide thickness of 1 nm. Device performance has also been analyzed at ldquoslow processrdquo corner to estimate the worst case degradation in performance matrices of the considered nano-FinFET.

QUANTUM AND COULOMB EFFECTS IN NANODEVICES

In state of the art devices, it is well known that quantum and Coulomb effects play significant role on the device operation. In this book chapter we demonstrate that a novel effective potential approach in conjunction with a Monte Carlo device simulation scheme can accurately capture the quantum-mechanical size quantization effects. Inclusion of tunneling within semi-classical simulation schemes is discussed in details. We also demonstrate, via proper treatment of the short-range Coulomb interactions, that there will be significant variation in device design parameters for devices fabricated on the same chip due to the presence of unintentional dopant atoms at random locations within the channel of alternative technology devices.

Influence of interface roughness on quantum transport in nanoscale FinFET

The authors utilize a fully quantum mechanical transport simulator based on the contact block reduction method to investigate the influence of interface roughness in nanoscale FinFET devices. In this work we treat interface roughness by creating a random deviation at the ideal Si∕SiO2 interface in real space and then solving the quantum transport problem fully self-consistently with the gates for the resulting device potential. We study the influence of interface roughness on device capacitance, drain current, and gate leakage for different regimes of operation. Our simulation results show that gate leakage is significantly affected by surface roughness, even though the average oxide thickness remains approximately the same. On the other hand, the on current is comparatively less sensitive to the interface roughness for FinFET devices with a narrow fin width. Furthermore, we find that the interface roughness significantly affects both the intrinsic switching speed and, especially, the cutoff frequency of FinFET with a narrow fin thickness.The authors utilize a fully quantum mechanical transport simulator based on the contact block reduction method to investigate the influence of interface roughness in nanoscale FinFET devices. In this work we treat interface roughness by creating a random deviation at the ideal Si∕SiO2 interface in real space and then solving the quantum transport problem fully self-consistently with the gates for the resulting device potential. We study the influence of interface roughness on device capacitance, drain current, and gate leakage for different regimes of operation. Our simulation results show that gate leakage is significantly affected by surface roughness, even though the average oxide thickness remains approximately the same. On the other hand, the on current is comparatively less sensitive to the interface roughness for FinFET devices with a narrow fin width. Furthermore, we find that the interface roughness significantly affects both the intrinsic switching speed and, especially, the cutoff frequency of ...

3D NEGF quantum transport simulator for modeling ballistic transport in nano FinFETs

Quantum effects play a dominant role in many of the state-of-the-art small size structures for which the applicability of the standard well-developed engineering tools based on a semi-classical transport description is very limited or even impossible. There are a number of methods developed by solid state theorists over the last several decades to address the issue of quantum transport. Among the most commonly used in nanostructure calculations schemes are the Wigner-function approach, the Pauli master equation, and the non-equilibrium Greens functions (NEGF). The growing popularity of the latest (sometimes referred to as the Keldysh or the Kadanoff-Baym) formalism is conditioned by its sound conceptual basis for the development of the new class of quantum transport simulators. We demonstrate in this work that the key to the successful application of the NEGF formalism to the 3D quantum transport problem in semiconductor nanostructures is the numerical efficiency of the contact block reduction (CBR) method. We also present some very important results from the 3D FinFET analysis, such as the importance of the third gate.

Ballistic Quantum-Mechanical Simulation of 10nm FinFET Using CBR Method

Simulating nanoscale devices with high accuracy, particularly towards 10nm feature sizes, requires highly efficient fully quantum mechanical simulators. In this work fully quantum mechanical simulator based on Contact Block Reduction (CBR) method has been used to investigate the behaviour of 10nm FinFET device in the ballistic regime of operation. Simulation results show the transformation from multiple channels into a single merged channel as the fin width is reduced gradually. Also we observe that short channel effects can be minimized by reducing the fin width which is evident from the device transfer characteristics presented in this paper.

Modeling FinFETs using non-equilibrium green's function formalism: Influence of interface-roughness on device characteristics

We utilize a fully quantum mechanical transport simulator based on the Contact Block Reduction (CBR) method to investigate the influence of interface roughness in nanoscale FinFET devices. In this work we treat interface roughness by creating a random deviation at ideal Si/SiO2 interface in real space, and then solving quantum transport problem fully self-consistently with the gates for the resulting device potential. We study the influence of interface roughness on device capacitance, drain current, and gate leakage for different regime of operation. Our simulation results show that gate leakage is significantly affected by surface roughness, even though the average oxide thickness remains approximately the same. On the other hand, the on-current is comparatively less sensitive to the interface roughness for FinFET devices with narrow fin width. Furthermore, we find that interface roughness significantly affects both the intrinsic switching speed and, especially, the cut-off frequency of FinFET with narrow fin thickness.