H. Martin Reekie

A hexapod robot modeled on the stick insect, Carausius morosus

Robot builders have often used insects as a source of inspiration when designing their mechanical systems, due to their ability to easily navigate uneven terrain, overcome or avoid obstacles, and adjust gaits based on traveling speed. Robotics has borrowed from nature with varying degrees of abstraction, from physical appearance to observed behaviours. This paper describes the design and construction of a robotic hexapod based on the stick insect, Carausius morosus. Physically, it is an 18.8:1 scale representation of the insect with 3-DoF legs. The to-scale design was chosen to provide similar physical attributes, such as joint and leg locations, sizes, and ranges-of-motion, which will allow more meaningful comparisons between robot performance and actual insect movements (as opposed to arbitrary hexapod designs). A custom-designed leg control board is responsible for deciding leg joint movements based on a model of the neurobiological systems identified in the insect. A distributed network of six boards will be used to control the legs based on internal parameters that can be modulated by descending commands or adaptively altered by ascending sensory signals when interacting with the environment. Our final aim in this work is to add a vision system to create depth maps, which will be used as an input to a learning system, coupled with the mechanical sensory system, such that terrain that triggers reflex actions can be associated with visual cues in order to predictively avoid obstacles and potholes.

Silicon superior colliculus for the integration of visual and auditory information with adaptive axon connection

Visual and auditory map alignment in the superior colliculus (SC) of the barn owl is important for its accurate localization of prey. The visual map, and hence the alignment, may be purposefully disturbed in a juvenile barn owl by fitting it with ocular prisms, and it is found that it can adapt its auditory map to this mismatch after several weeks training. In our previous SC model, the axon growing process is instructed by an inhibitory network, the strength of which is adjusted using the neural structures involved in spatial localization. Based on this model, a mixed signal integrated circuit of the SC has been designed, and simulation results are consistent with those found by biological experiment. This new model makes possible artificial networks capable of eliminating the disparity between the visual and auditory maps.

Fully Cascadable Analogue Synapses Using Distributed Feedback

We have solved the problems of cascadability and process variation for analogue VLSI neural networks. A synapse design is proposed,based on op-amp feedback,which avoids these problems. Other supporting circuitry which automatically determines bias voltages is also discussed. The circuits have been fully simulated and are now being fabricated.

Pulse-Firing VLSI Neural Circuits for Fast Image Pattern Recognition

Neural networks are identified as an effective means of performing pattern recognition on image data. To take advantage of the parallelism inherent in such architectures, an analogue CMOS VLSI circuit has been developed. This device consists of novel pulse-firing neurons and synapses. The neurons are current controlled oscillators, which deplete their own input activity whenever a pulse is fired, in a manner similar to biological neurons. The synapses use neural voltage pulses to create pulsed current outputs. The magnitude of these outputs is determined by the synaptic weight voltage. When configured as a multi-layered perceptron, the neural circuit will facilitate the “real-tune” labelling of regions in segmented images.

Working Analogue Pulse-Firing Neural Network Chips

The design of a programmable analogue pulse width modulation synapse is described for use in pulse-firing neural networks. Results from working VLSI devices are presented. A scheme for communicating large numbers of neural states between chips is proposed. The design of process independent pulse-firing neurons for use in networks and inter-chip communications are given.

STF behaviour in optimised for ELD cascaded CT Delta-Sigma Modulators

This paper looks at the Signal Transfer Function (STF) behaviour of cascaded Continuous-Time Delta-Sigma Modulators (CTDSMs) and how the flattening technique proposed by De Maeyer et al. can be used to reduce the effect of interfering signals and performance degradation for a subset of Excess Loop Delays (ELDs). Furthermore it will be shown that the noise-shaping performance of a CTDSM can be improved by optimising to take advantage of the ELD induced loop-filter order increase at the expense of the Anti-Alias Filter (AAF) response. Example cascades for two repeated second-order sections are presented which show that STF flattening and ELD optimisation offer improved performance over that of the undelayed system.

Other Integrated Circuit Technologies

Thus far, this book has dealt exclusively with silicon MOS integrated circuits as this represents the majority of Application-Specific Integrated Circuits. However, the first semiconductor amplifier was a bipolar transistor and this device has not become significantly less important with the passing of the years. There is also considerable investment in a relatively recent technology known as’ silicon-on-Insulator’ (SOI). This is fundamentally an MOS process but the substrate is a wafer made of some insulating material. There are a number of materials which can be used for the substrate but the most promising to date is sapphire and, not unreasonably, this variant of SOI is known as Silicon-on-Sapphire (SOS). Silicon is not the only semiconductor known to science. There has always been germanium and, holding great promise for the future, there are the so-called III–V compounds such as gallium arsenide. These have some advantages over silicon.

Introduction to MOS (Metal-Oxide-Semiconductor) Devices and Logic

This chapter presents a straightforward treatment of the principles of operation of MOS (Metal-Oxide-Silicon) transistors. While it is necessary to ensure that excessive simplicity (at the expense of correctness) is avoided, the essential aspects of MOS device behaviour should not be obscured by overly rigorous physics. The Bibliography at the end of the book suggests sources where the derivation and discussion of the full MOS device equations may be found. At present, however, to allow us to make a first attempt at MOS Integrated Circuit (IC) Design, we will concentrate on simplified forms of such equations as are essential to the discussion. In addition we shall use a 5V power supply. This is a typical value but is not immutable.