H. Nishio

A Digitally Controlled DC-DC Converter Module with a Segmented Output Stage for Optimized Efficiency

This paper presents a 4 MHz, 0.9 W digitally controlled DC-DC converter with a miniature planar inductor for 1.8 V portable devices. In applications such as cellular phones, it is crucial to achieve high conversion efficiency over the entire load range. A binary-weighted segmented power stage is used to dynamically optimize the converter efficiency by reducing the gate-drive losses at mid-to-light loads. An all-digital segment controller based on a load current estimator is demonstrated. This approach is most effective in the mid-load range, where the losses are reduced by 33 %, corresponding to an efficiency improvement of 7.5 % at Vin = 4.2 V. A peak efficiency of 89 % is achieved at fs = 4 MHz and Vin = 2.7 V

A segmented gate driver IC for the reduction of IGBT collector current over-shoot at turn-on

In this paper, a segmented IGBT gate driver IC for mitigating IGBT turn-on I_C over-shoot is presented. The proposed IC is fabricated using TSMCs 0.18 μm BCD Gen-2 process. Unlike existing I_C over-shoot reduction techniques, the proposed technique does not require significant additional external components or an increase in turn-on energy. During turn-on, the gate driver is controlled such that (dV_GE/dt) is kept low as current is transferred from the FWD to the IGBT and kept high at all other times. The ideal timing of (dV_GE/dt) transitions could vary between IGBT devices, age, temperature, etc. A feedback system is used to correct for these variances. A 37% reduction in I_C overshoot is achieved while maintaining the same E_ON. A 54% reduction in E_ON is achieved for the same I_C overshoot. Finally, a 15.5 dBm reduction in CEMI is observed when compared to operation with a constant R_OUT and similar Eon.

Dynamic gate resistance control for current balancing in parallel connected IGBTs

In high power applications, switching devices such as MOSFETs and IGBTs must often be connected in parallel in order to provide higher current capability. However, the current imbalance of parallel connected IGBTs due to stray inductance, variations in device characteristics and asymmetric PCB layout, necessitates de-rating of the IGBTs. This deliberate de-rating is required in order to ensure the IGBTs function within their Safe-Operating-Area. Unfortunately, de-rating also leads to an increase in cost, size and complexity of the overall power electronics system. A current balancing method for parallel connected IGBTs using a dynamically adjustable gate driving resistance (Rg_dyanmic) is presented in this paper. Experimental results are achieved by measuring the current distribution between two parallel connected IGBTs (rated at 600V, 90A). These experimental results indicate an improvement in average current imbalance of 74% and 65% for the turn on and off periods, respectively.

A digital predictive on-line energy optimization scheme for dc-dc converters

This work presents a novel energy conservation technique based on predicting the load current of a DC-DC converter that may feed a variety of loads, such as speakers and displays. The predicted load cnrrent is used to dynamically adjust the size of the output stage transistors and to switch into PFM mode to maximize the instantaneous converter efficiency. By using a segmented output stage, the trade-off between the gate drive losses and RMS conduction losses can be continuously optimized over the full load current range. The technique relies on the fact that the digital data stream which feeds modern electronic loads can be processed in real-time to predict the load cnrrent without relying on explicit cnrrent sensing or slow steady-state calibration techniques. The experimental prototype includes a digitally controlled 3.6V-to-1.8V DC-DC converter with an integrated segmented power stage IC operating at 4 MHz. A high-fidelity class-D audio amplifier acts as the DC-DC converter load. The results show a good agreement between the digitally predicted and actual DC-DC converter load current. The total energy consumed for three music pieces was reduced by up to 38% using the automatic mode/segment control technique. The fully digital efficiency optimization technique is well suited to future monolithic integration in advanced CMOS processes.

Reduction of conducted electromagnetic interference in SMPS using programmable gate driving strength

A gate driver IC with programmable driving strength to reduce conducted electromagnetic interference (CEMI) in SMPS is presented in this paper. The solution presented is to dynamically adjust the gate driving strength (output resistance Rout) at the arrival of each gate pulse to minimize CEMI while maintaining low switching loss. Dynamically adjusting Rout is not possible with conventional gate driver designs. A segmented gate driver is designed and fabricated in the AMS 0.35μm 40V HVCMOS process. Unlike snubber circuits, the proposed method does not require extra discrete components or wasted energy. Experimental results indicate up to a 7dBμV improvement in peak CEMI between 20 MHz and 30 MHz.

Digitally controlled integrated DC-DC converters with fast transient response

Fast load transient response and high power conversion efficiency in DC-DC converters have conflicting requirements on the size of the inductor. In this paper, an integrated point-of-load (POL) DC-DC converter with an smaller auxiliary output stage added in parallel to the main output switching stage to help reduce the output voltage deviation during load transient is investigated. The transistor sizing of the auxiliary output stage in relation to the main output stage is studied through analysis and simulation of a 12 V to 1 V, 3 W, buck converter. The auxiliary output stage performs well with transistors occupying as little as 5% the area of the main output stage.

Current balancing control for parallel connected IGBTs using programmable gate driver output resistance

A gate driver IC with programmable output resistance (Rout) capable of performing current balancing for parallel connected IGBTs is presented in this paper. This novel method is to dynamically adjust the gate driver Rout to minimize the difference in the turn-on/off delay times between parallel connected IGBTs. The programmable gate driver Rout is implemented using a segmented output stage technique. This gate driver IC is designed and fabricated using TSMCs 0.18μm BCD Gen-2 process. Experimental results are obtained by measuring the current distribution between two parallel connected IGBTs (600V, 90A). These results indicate an improvement in average current imbalance of 89% and 98% for the turn-on and off periods, respectively.

Integrated DC-DC converter with an auxiliary output stage for transient suppression

In this paper, the transistor sizing of an auxiliary output stage in a digitally controlled transient suppression system for fully integrated point-of-load (POL) DC-DC converters is investigated. The auxiliary output stage is added in parallel to the main output switching stage to help reduce output voltage deviation during load transient. The sizing of the auxiliary output stage in relation to the main output stage is studied through analysis and simulation of a 3 W, 12 V to 1 V buck converter. The auxiliary output stage performs well with transistors occupying as little as 5% the area of the main output stage.

An IGBT gate driver IC with collector current sensing

In this paper, an IGBT gate driver IC with a collector current sensing circuit and an on-chip CPU for digital control is presented. The IC is fabricated using TSMCs 0.18 μm BCD Gen-2 process. This technique is based on the unique Miller plateau relationship between the gate current and collector current (Ig and IC) for a particular gate resistance (Rg), and allows for a cycle by cycle measurement of IC during both turn-on and turn-off transients. Together with a dedicated and simple on-chip stack-based CPU, this technique can potentially provide collector current regulation without any extra discrete component. This technique only monitors the low voltage signal at the gate terminal, without the need to handle any high voltage signal on the collector/load side. Measurements have been carried out using a double pulse test setup. An accuracy within ±1 A is achieved over the current ranges between 1 to 30 A for turn-on and 1 to 50 A for turn-off.