Wai Tung Ng

Interfacial growth in HfOxNy gate dielectrics deposited using [(C2H5)2N]4Hf with O2 and NO

The interface growth by oxygen diffusion has been investigated for 5 nm thick HfOxNy gate-quality dielectric films deposited on Si(100) by low-pressure pulsed metalorganic chemical vapor deposition. Analysis by x-ray photoelectron spectroscopy of the films deposited using the precursor tetrakis (diethylamido) hafnium with O2 showed that the films contained 4 at. % nitrogen. This increased to 11 at. % N when NO was used as the oxidant. Significant growth of the interface layer was observed for films exposed to air at ambient temperature and lower rates of growth were observed for vacuum annealed films and those with the higher N content. For films annealed in O2 at temperatures in the range 600–900 °C, the activation energies of the interfacial growth were 0.36 and 0.25 eV for N concentrations of 11 and 4 at. %, respectively. The results were interpreted in terms of atomic oxygen formation in the bulk and reaction at the interface. The increase in N incorporation from 4 to 11 at. % increases the crystalliz...

Precision gate drive timing in a zero-voltage-switching DC-DC converter

This paper presents the design and implementation of an integrated low-voltage power conversion controller capable of delivering MOSFET gate-drive signals to on-chip power transistors with precision timing. Analog dead-time-locked-loops (DTLL) are used to realize an accurate analog deadtime controller with fast error rejection in a fixed frequency zero-voltage-switching quasi-square-wave (ZVS-QSW) buck converter.

Digitally Controlled Current-Mode DC–DC Converter IC

The main focus of this paper is the implementation of mixed-signal peak current mode control in low-power dc-dc converters for portable applications. A DAC is used to link the digital voltage loop compensator to the analog peak current mode loop. Conventional DAC architectures, such as flash or ΔΣ are not suitable due to excessive power consumption and limited bandwidth of the reconstruction filter, respectively. The charge-pump based DAC (CP-DAC) used in this work has relatively poor linearity compared to more expensive DAC topologies; however, this can be tolerated since the linearity has a minor effect on the converter dynamics as long as the limit-cycle conditions are met. The CP-DAC has a guaranteed monotonic behavior from the digital current command to the peak inductor current, which is essential for maintaining stability. A buck converter IC, which was fabricated in a 0.18 μm CMOS process with 5 V compatible transistors, achieves a response time of 4 μs at fs=3 MHz and Vout=1 V, for a 200 mA load-step. The active area of the controller is only 0.077 mm2, and the total controller current-draw, which is heavily dominated by the on-chip senseFET current-sensor, is below 250 μA for a load current of Iout=50 mA.

A Digitally Controlled DC-DC Converter Module with a Segmented Output Stage for Optimized Efficiency

This paper presents a 4 MHz, 0.9 W digitally controlled DC-DC converter with a miniature planar inductor for 1.8 V portable devices. In applications such as cellular phones, it is crucial to achieve high conversion efficiency over the entire load range. A binary-weighted segmented power stage is used to dynamically optimize the converter efficiency by reducing the gate-drive losses at mid-to-light loads. An all-digital segment controller based on a load current estimator is demonstrated. This approach is most effective in the mid-load range, where the losses are reduced by 33 %, corresponding to an efficiency improvement of 7.5 % at Vin = 4.2 V. A peak efficiency of 89 % is achieved at fs = 4 MHz and Vin = 2.7 V

An optimized RESURF LDMOS power device module compatible with advanced logic processes

An advanced optimized RESURF LDMOS device intended for use in low side applications and suitable for integration into advanced CMOS and BiCMOS processes is described. Devices with 84 V and 97 V breakdown voltages have been modeled and fabricated with excellent specific on-resistance performance at CMOS level gate drives. Specific on-resistance of 2.0 m Omega .cm/sup 2/ at 97 V represents the best performance in this voltage class.<<ETX>>

Predictive Efficiency Optimization for DC–DC Converters With Highly Dynamic Digital Loads

This paper presents a novel technique and system for increasing the efficiency of dc-dc converters that supply dynamic electronic loads, such as modern audio and video equipment and other devices whose power consumption largely depends on the digital data they process. The optimization does not require a current-measurement circuit and is well-suited to portable applications. It is based on a real-time prediction of the dc-dc converter output current from easily accessible digital data streams present in the targeted loads. The result of the prediction is used for dynamic adjustment of the power-stage transistor size and/or for switching into pulse-frequency-mode of output voltage regulation, in order to maximize the instantaneous converter efficiency on-the-fly. The use of a segmented power-stage allows the effective power-transistor size to be changed on-the-fly, and the tradeoff between the gate-drive and rms conduction losses is continuously optimized over the full range of operation. The effectiveness of the optimization is demonstrated on an experimental system, including a 1-W digitally controlled 4-MHz, 3.6 V-1.8 V buck converter with an integrated segmented power-stage and a digital high-fidelity class-D audio amplifier acting as the digital load. The results show a good agreement between the digitally predicted and actual dc-dc converter load current, as well as a reduction in total energy consumption of up to 38%.

A Segmented Digital Pulse Width Modulator with Self-Calibration for Low-Power SMPS

The next-generation, digitally controlled DC-DC converters require a high frequency, high resolution, low power and area efficient digital pulse width modulator (DPWM). This paper introduces a self-calibrated segmented DPWM that uses a delay-locked loop to calibrate adjacent delay segments. An 8-bit prototype designed in a 0.13-μm CMOS process operates at a switching frequency of 11.6 MHz, draws 190μA from a 1.2 V supply and occupies only 0.0075 mm2.

A low-power mixed-signal current-mode DC-DC converter using a one-bit /spl Delta//spl Sigma/ DAC

This work describes a dual-mode mixed-signal peak current-mode controller for high-frequency DC-DC converters. The simple controller provides peak-current protection, inherent low audio susceptibility, and is suitable for portable applications. The voltage feedback loop is implemented using a windowed ADC and a digital PI compensator based on lookup tables. The analog current command used in traditional current-mode controllers is generated by a 2nd order one-bit /spl Delta//spl Sigma/ DAC. The dual-mode controller automatically adjusts the DAC sampling frequency based on the digital error signal magnitude. The mixed-signal control strategy is experimentally verified on a 5V-to-1.5V 1 MHz buck converter prototype that exhibits a settling time of under 50 /spl mu/s.

Variable output, soft-switching DC/DC converter for VLSI dynamic voltage scaling power supply applications

The implementation of a low-voltage zero-voltage-switching quasi-square-wave (ZVS-QSW) buck converter capable of meeting the future challenges of low-voltage VRMs is presented. By eliminating switching losses, high-efficiency operation at switching frequencies beyond 1 MHz is achieved. The design uses novel high-speed dead-time-locked-loops with fast dead-time error rejection to ensure zero-voltage-switching under dynamic loads and variable output conditions. The ZVS-QSW converter, which was implemented in a mixed-signal 0.18 m CMOS process, has a measured efficiency of 82% at 5 MHz with a 1.4 V output. The ZVS-QSW converter is intended to supply the next generation VLSI chips with a variable supply voltage for dynamic voltage scaling (DVS) applications. DVS refers to the real-time scaling of the supply voltage to the VLSI chip to minimize dynamic power consumption, while satisfying a variable target clock frequency. Several DVS strategies are examined, and it is shown that DVS can be applied to the ZVS-QSW converter using a dual-mode configuration. An experimental DVS test-bench was developed using a state-of-the-art Xilinx CPLD capable of operating from 1.35 V to 1.8 V. The PID controlled DVS system achieves the maximum V/sub DD/ transition in 22 /spl mu/s.

Lateral high-speed bipolar transistors on SOI for RF SoC applications

This paper introduces a novel silicon-on-insulator (SOI) lateral radio-frequency (RF) bipolar transistor. The fabrication process relies on polysilicon side-wall-spacer (PSWS) to self-align the base contact to the intrinsic base. The self-aligned base and emitter regions greatly reduce the parasitic components. In this unique design, the critical dimensions are not limited by lithography resolution. With the control of the SOI film thickness or SWS width, the device can be optimized for higher speed, gain, breakdown, or current drive capability. Furthermore, with no additional mask, both common-emitter and common-collector layout configurations can be realized, providing more flexibility to the circuit design and more compact layout. The experimental f/sub T//f/sub max/ of the high-speed device are 17/28 GHz, the second fastest reported f/sub T/ for lateral bipolar junction transistors (LBJT) so far. As for the high-voltage device, the measured f/sub T//f/sub max/ of 12/30 GHz and BV/sub CEO/ of over 25 V produces a Johnsons product well above 300 GHz /spl middot/V. This figure is currently the closest reported data to the Johnsons limit for lateral BJTs. This technology can easily be integrated with CMOS on SOI. Therefore, it is feasible to build fully complimentary bipolar and MOS transistors on a single SOI substrate to form a true complementary-BiCMOS process. This silicon-based lateral SOI-BJT technology is a promising candidate for realizing future RF SoC applications.