H.R. Harris

Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning

An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. Vt tuning depends on rare earth (RE) type and diffusion in Si∕SiOx∕HfSiON∕REOx/metal gated nFETs as follows: Sr<Er<Sc+Er<La<Sc<none. This Vt ordering is very similar to the trends in dopant electronegativity (EN) (dipole charge transfer) and ionic radius (r) (dipole separation) expected for a interfacial dipole mechanism. The resulting Vt dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).

Band-Engineered Low PMOS V T with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

Using strained SiGe on Si, the threshold voltage of high k PMOS devices is reduced by as much as 300 mV. The 80 nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high kappa and metal gates for 32 nm node and beyond.

Thermally Stable N-Metal Gate MOSFETs Using La-Incorporated HfSiO Dielectric

We report a thermally stable N-metal process in which surface passivation of HfSiO dielectric using thin layers of La₂O₃, deposited by either MBE or PVD, significantly shifts the metal gate effective work function toward the Si conduction band edge. Well-behaved transistors with L_g down to 70 nm have been fabricated with threshold voltage of 0.25V, mobility up to 92% of the universal SiO₂ mobility, and T_inv ~1.6 nm

Improved Ge Surface Passivation With Ultrathin

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiO_X passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm²middotV^-1middots^-1 at 0.05 MV/cm-a 2times enhancement over the universal Si/SiO₂ mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an I_ON/I_OFF ratio of 3times10³ without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface

\hbox{SiO}_{X}

This letter correlates fast transient charging (FTC) in high-k gate dielectrics to variations in its oxygen content. Analysis of electrical and physical data suggests that the observed enhancement of FTC may be caused by reduction of the oxygen content in the high-k film due to O scavenging process induced by the HfSix metal electrode. A hypothesis correlating O scavenging from the high-k dielectric to O vacancy formation, which contributes to FTC, is proposed

Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack

The effective work function (EWF) extracted on terraced oxide structures by capacitance-voltage-based techniques was compared with the work function calculated from the barrier height extracted by current-voltage measurements. The results show a reasonable correlation-within /spl plusmn/ 0.1 eV-in the EWF values for various metal gate electrodes, validating both techniques for EWF extraction.

On Oxygen Deficiency and Fast Transient Charge-Trapping Effects in High-

It is shown that the work function of Ta1−xAlxNy depends on the electrode and gate dielectric compositions. Specifically, the work function of Ta1−xAlxNy increased with SiO2 content in the gate dielectric, reaching as high as 5.0eV on SiO2; the work function was nearly 400mV smaller on HfO2. In addition, the work function decreased with increasing nitrogen content in the Ta1−xAlxNy metal gate. Increasing Al concentration increased the work function up to about 15% Al, but the work function decreased for higher Al concentrations. Chemical analysis shows that Al–O bonding at the interface correlates with the observed work function values.

k

We demonstrate for the first time that both SiGe and Ge channel with high-k/metal gate stack pMOSFETs show similar uniaxial stress enhanced drive current as Si which is expected from k.p calculations. We also demonstrate experimentally that pMOSFETs with strained quantum wells (QW) in the Si-Ge system exhibited high performance and low off-state leakage comparable to optimized gate stacks on Si. These results significantly hasten the feasibility of realizing SiGe or Ge channel pMOSFETs for 22 nm and beyond.

Dielectrics

The evaluation of the instability of the threshold voltage in high-k gate stack structures is of paramount importance in assessing the reliability of next generation FETs. In the case of SiO/sub 2/ gate dielectric PMOS transistors, this instability, known as NBTI, has been attributed to the hole-assisted dissociation of the hydrogen that passivates dangling bonds at the interface with the Si substrate. However, in hafnium-based gate stacks, evaluation of the NBTI phenomenon is complicated by the charge trapping process, which was shown to occur reversibly on pre-existing defects in NMOS devices. In this report, we examine the cycle dependence of negative gate stress and positive gate de-trapping on PMOS high-k/metal gate transistors. The threshold voltage instability is found to be due mainly to charge trapping and de-trapping of both shallow and deep electron traps in the high-k dielectric. There is minimal change in the interface quality with negative bias stress, and a similar detrapping nature is found for NMOS devices with a comparable electric field.

Comparison of effective work function extraction methods using capacitance and current measurement techniques

High-performance sub-60 nm Si/SiGe (Ge:~75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high-kappa/metal gate stacks with ~1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length (<i>L</i> _g) devices demonstrate not only controlled short channel effects, but also an excellent on-off current (<i>I</i> _on/<i>I</i> _off) ratio (~5times10⁴ 55-nm <i>L</i> _g). The intrinsic gate delay of these heterostructures is ~3 ps at <i>I</i> _on/<i>I</i> _off~10⁴. OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short <i>L</i> _g devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.