Prashant Majhi

Si tunnel transistors with a novel silicided source and 46mV/dec swing

We report a novel tunneling field effect transistor (TFET) fabricated with a high-k/metal gate stack and using nickel silicide to create a special field-enhancing geometry and a high dopant density by dopant segregation. It produces steep subthreshold swing (SS) of 46mV/dec and high ION/IOFF ratio (∼108) and the experiment was successfully repeated after two months. Its superior operation is explained through simulation. For the first time convincing statistical evidence of sub-60mV/dec SS is presented. More than 30% of the devices show sub-60mV/dec SS after systemic data quality checks that screen out unreliable data.

Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning

An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. Vt tuning depends on rare earth (RE) type and diffusion in Si∕SiOx∕HfSiON∕REOx/metal gated nFETs as follows: Sr<Er<Sc+Er<La<Sc<none. This Vt ordering is very similar to the trends in dopant electronegativity (EN) (dipole charge transfer) and ionic radius (r) (dipole separation) expected for a interfacial dipole mechanism. The resulting Vt dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).

Work function engineering using lanthanum oxide interfacial layers

A La2O3 capping scheme has been developed to obtain n-type band-edge metal gates on Hf-based gate dielectrics. The viability of the technique is demonstrated using multiple metal gates that normally show midgap work function when deposited directly on HfSiO. The technique involves depositing a thin interfacial of La2O3 on a Hf-based gate dielectric prior to metal gate deposition. This process preserves the excellent device characteristic of Hf-based dielectrics, but also allows the realization of band-edge metal gates. The effectiveness of the technique is demonstrated by fabricating fully functional transistor devices. A model is proposed to explain the effect of La2O3 capping on metal gate work function.

Wafer-scale, sub-5 nm junction formation by monolayer doping and conventional spike annealing.

We report the formation of sub-5 nm ultrashallow junctions in 4 in. Si wafers enabled by the molecular monolayer doping of phosphorus and boron atoms and the use of conventional spike annealing. The junctions are characterized by secondary ion mass spectrometry and noncontact sheet resistance measurements. It is found that the majority ( approximately 70%) of the incorporated dopants are electrically active, therefore enabling a low sheet resistance for a given dopant areal dose. The wafer-scale uniformity is investigated and found to be limited by the temperature homogeneity of the spike anneal tool used in the experiments. Notably, minimal junction leakage currents (<1 microA/cm(2)) are observed that highlights the quality of the junctions formed by this process. The results clearly demonstrate the versatility and potency of the monolayer doping approach for enabling controlled, molecular-scale ultrashallow junction formation without introducing defects in the semiconductor.

InGaAs metal-oxide-semiconductor capacitors with HfO2 gate dielectric grown by atomic-layer deposition

The influence of various process conditions on the structural integrity and electrical properties of Al∕HfO2∕p-In0.13Ga0.87As metal-oxide-semiconductor capacitors was investigated. Room temperature capacitance voltage measurements revealed postdielectric deposition anneal reduced hysteresis by more than 0.5V and sulfur passivation of InGaAs improved the capacitance frequency dispersion properties as well as reduced interface trap density. At V=VFB−1V, the leakage current densities ∼1.3×10−7, 0.4×10−6, and 1.3×10−6A∕cm2 were measured in devices with annealed HfO2 (110 and 32A) and sulfur-passivated InGaAs (110A unannealed HfO2), respectively. Transmission electron microscopy revealed sharp epitaxial InGaAs/crystalline HfO2 and GaAs∕InGaAs interfaces.

Nanoscale doping of InAs via sulfur monolayers

One of the challenges for the nanoscale device fabrication of III-V semiconductors is controllable postdeposition doping techniques to create ultrashallow junctions. Here, we demonstrate nanoscale, sulfur doping of InAs planar substrates with high dopant areal dose and uniformity by using a self-limiting monolayer doping approach. From transmission electron microscopy and secondary ion mass spectrometry, a dopant profile abruptness of ∼3.5 nm/decade is observed without significant defect density. The n+/p+ junctions fabricated by using this doping scheme exhibit negative differential resistance characteristics, further demonstrating the utility of this approach for device fabrication with high electrically active sulfur concentrations of ∼8×1018 cm−3.

Characteristics and mechanism of tunable work function gate electrodes using a bilayer metal structure on SiO/sub 2/ and HfO/sub 2/

In this letter, we investigate a method to adjust the gate work function of an MOS structure by stacking two metals with different work functions. This method can provide work function tunability of approximately 1 eV as the bottom metal layer thickness is increased from 0 to about 10 nm. This behavior is demonstrated with different metal combinations on both SiO/sub 2/ and HfO/sub 2/ gate dielectrics. We use capacitance-voltage (C-V) characteristics to investigate the effect of different annealing conditions and different metal/metal bilayer couples on the work function. By comparing the as-deposited and annealed films, and by comparing with metals that are relatively inert with each other, we deduce that the work function tuning behavior likely involves metal/metal interdiffusion.

In0.53Ga0.47As based metal oxide semiconductor capacitors with atomic layer deposition ZrO2 gate oxide demonstrating low gate leakage current and equivalent oxide thickness less than 1nm

The paper demonstrates properties of metal oxide semiconductor capacitors fabricated on molecular beam epitaxial In0.53Ga0.47As wafers with the atomic layer deposition ZrO2 gate oxide. The equivalent oxide thickness of 0.8nm was obtained for 5nm thick ZrO2, while the gate leakage current density at VFB+1V was as low as 0.1A∕cm2. Sensitivity of capacitance-voltage characteristics to the metal gate work function along with low frequency dispersion of ∼5%/decade served as a strong evidence of a nonpinned Fermi level at the oxide-InGaAs interface. Both electrical and structural properties remain stable up to 800°C.

Prospect of tunneling green transistor for 0.1V CMOS

Well designed tunneling green transistor may enable future VLSIs operating at 0.1V. Sub-60mV/decade characteristics have been convincingly demonstrated on 8″ wafers. Large ION at low VDD are possible according to TCAD simulations but awaits verification. VDD scaling will greatly benefit from low (effective) band gap energy, which may be provided by type II heterojunctions of Si/Ge or compound semiconductors.

Self-aligned n-channel metal-oxide-semiconductor field effect transistor on high-indium-content In0.53Ga0.47As and InP using physical vapor deposition HfO2 and silicon interface passivation layer

In this work, we present the electrical and material characteristics of TaN∕HfO2∕In0.53Ga0.47As and InP substrate metal-oxide-semiconductor capacitors and self-aligned n-channel metal-oxide-semiconductor field effect transistor (n-MOSFET) with physical vapor deposition Si interface passivation layer. Excellent electrical characteristics, thin equivalent oxide thickness (∼1.7nm), and small frequency dispersion (<2%) were obtained. n-channel high-k InGaAs- and InP-MOSFETs with good transistor behavior and good split capacitance-voltage (C-V) characteristics on In0.53Ga0.47As and InP substrates have also been demonstrated.